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path: root/drivers/media/video/cx18/cx18-irq.c
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Diffstat (limited to 'drivers/media/video/cx18/cx18-irq.c')
-rw-r--r--drivers/media/video/cx18/cx18-irq.c96
1 files changed, 57 insertions, 39 deletions
diff --git a/drivers/media/video/cx18/cx18-irq.c b/drivers/media/video/cx18/cx18-irq.c
index 360330f5463f..5fbfbd0f1493 100644
--- a/drivers/media/video/cx18/cx18-irq.c
+++ b/drivers/media/video/cx18/cx18-irq.c
@@ -29,8 +29,20 @@
#include "cx18-mailbox.h"
#include "cx18-vbi.h"
#include "cx18-scb.h"
+#include "cx18-dvb.h"
-#define DMA_MAGIC_COOKIE 0x000001fe
+void cx18_work_handler(struct work_struct *work)
+{
+ struct cx18 *cx = container_of(work, struct cx18, work);
+ if (test_and_clear_bit(CX18_F_I_WORK_INITED, &cx->i_flags)) {
+ struct sched_param param = { .sched_priority = MAX_RT_PRIO-1 };
+ /* This thread must use the FIFO scheduler as it
+ * is realtime sensitive. */
+ sched_setscheduler(current, SCHED_FIFO, &param);
+ }
+ if (test_and_clear_bit(CX18_F_I_WORK_HANDLER_DVB, &cx->i_flags))
+ cx18_dvb_work_handler(cx);
+}
static void epu_dma_done(struct cx18 *cx, struct cx18_mailbox *mb)
{
@@ -67,17 +79,11 @@ static void epu_dma_done(struct cx18 *cx, struct cx18_mailbox *mb)
if (buf) {
cx18_buf_sync_for_cpu(s, buf);
if (s->type == CX18_ENC_STREAM_TYPE_TS && s->dvb.enabled) {
- /* process the buffer here */
- CX18_DEBUG_HI_DMA("TS recv and sent bytesused=%d\n",
- buf->bytesused);
-
- dvb_dmx_swfilter(&s->dvb.demux, buf->buf,
+ CX18_DEBUG_HI_DMA("TS recv bytesused = %d\n",
buf->bytesused);
- cx18_buf_sync_for_device(s, buf);
- cx18_vapi(cx, CX18_CPU_DE_SET_MDL, 5, s->handle,
- (void __iomem *)&cx->scb->cpu_mdl[buf->id] - cx->enc_mem,
- 1, buf->id, s->buf_size);
+ set_bit(CX18_F_I_WORK_HANDLER_DVB, &cx->i_flags);
+ set_bit(CX18_F_I_HAVE_WORK, &cx->i_flags);
} else
set_bit(CX18_F_B_NEED_BUF_SWAP, &buf->b_flags);
} else {
@@ -109,7 +115,7 @@ static void epu_debug(struct cx18 *cx, struct cx18_mailbox *mb)
CX18_INFO("FW version: %s\n", p - 1);
}
-static void hpu_cmd(struct cx18 *cx, u32 sw1)
+static void epu_cmd(struct cx18 *cx, u32 sw1)
{
struct cx18_mailbox mb;
@@ -125,12 +131,31 @@ static void hpu_cmd(struct cx18 *cx, u32 sw1)
epu_debug(cx, &mb);
break;
default:
- CX18_WARN("Unexpected mailbox command %08x\n", mb.cmd);
+ CX18_WARN("Unknown CPU_TO_EPU mailbox command %#08x\n",
+ mb.cmd);
break;
}
}
- if (sw1 & (IRQ_APU_TO_EPU | IRQ_HPU_TO_EPU))
- CX18_WARN("Unexpected interrupt %08x\n", sw1);
+
+ if (sw1 & IRQ_APU_TO_EPU) {
+ cx18_memcpy_fromio(cx, &mb, &cx->scb->apu2epu_mb, sizeof(mb));
+ CX18_WARN("Unknown APU_TO_EPU mailbox command %#08x\n", mb.cmd);
+ }
+
+ if (sw1 & IRQ_HPU_TO_EPU) {
+ cx18_memcpy_fromio(cx, &mb, &cx->scb->hpu2epu_mb, sizeof(mb));
+ CX18_WARN("Unknown HPU_TO_EPU mailbox command %#08x\n", mb.cmd);
+ }
+}
+
+static void xpu_ack(struct cx18 *cx, u32 sw2)
+{
+ if (sw2 & IRQ_CPU_TO_EPU_ACK)
+ wake_up(&cx->mb_cpu_waitq);
+ if (sw2 & IRQ_APU_TO_EPU_ACK)
+ wake_up(&cx->mb_apu_waitq);
+ if (sw2 & IRQ_HPU_TO_EPU_ACK)
+ wake_up(&cx->mb_hpu_waitq);
}
irqreturn_t cx18_irq_handler(int irq, void *dev_id)
@@ -140,43 +165,36 @@ irqreturn_t cx18_irq_handler(int irq, void *dev_id)
u32 sw2, sw2_mask;
u32 hw2, hw2_mask;
- spin_lock(&cx->dma_reg_lock);
-
+ sw1_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI);
+ sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & sw1_mask;
+ sw2_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI);
+ sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & sw2_mask;
hw2_mask = cx18_read_reg(cx, HW2_INT_MASK5_PCI);
hw2 = cx18_read_reg(cx, HW2_INT_CLR_STATUS) & hw2_mask;
- sw2_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU_ACK;
- sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & sw2_mask;
- sw1_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU;
- sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & sw1_mask;
- cx18_write_reg(cx, sw2&sw2_mask, SW2_INT_STATUS);
- cx18_write_reg(cx, sw1&sw1_mask, SW1_INT_STATUS);
- cx18_write_reg(cx, hw2&hw2_mask, HW2_INT_CLR_STATUS);
+ if (sw1)
+ cx18_write_reg_expect(cx, sw1, SW1_INT_STATUS, ~sw1, sw1);
+ if (sw2)
+ cx18_write_reg_expect(cx, sw2, SW2_INT_STATUS, ~sw2, sw2);
+ if (hw2)
+ cx18_write_reg_expect(cx, hw2, HW2_INT_CLR_STATUS, ~hw2, hw2);
if (sw1 || sw2 || hw2)
CX18_DEBUG_HI_IRQ("SW1: %x SW2: %x HW2: %x\n", sw1, sw2, hw2);
/* To do: interrupt-based I2C handling
- if (hw2 & 0x00c00000) {
+ if (hw2 & (HW2_I2C1_INT|HW2_I2C2_INT)) {
}
*/
- if (sw2) {
- if (sw2 & (cx18_readl(cx, &cx->scb->cpu2hpu_irq_ack) |
- cx18_readl(cx, &cx->scb->cpu2epu_irq_ack)))
- wake_up(&cx->mb_cpu_waitq);
- if (sw2 & (cx18_readl(cx, &cx->scb->apu2hpu_irq_ack) |
- cx18_readl(cx, &cx->scb->apu2epu_irq_ack)))
- wake_up(&cx->mb_apu_waitq);
- if (sw2 & cx18_readl(cx, &cx->scb->epu2hpu_irq_ack))
- wake_up(&cx->mb_epu_waitq);
- if (sw2 & cx18_readl(cx, &cx->scb->hpu2epu_irq_ack))
- wake_up(&cx->mb_hpu_waitq);
- }
+ if (sw2)
+ xpu_ack(cx, sw2);
if (sw1)
- hpu_cmd(cx, sw1);
- spin_unlock(&cx->dma_reg_lock);
+ epu_cmd(cx, sw1);
+
+ if (test_and_clear_bit(CX18_F_I_HAVE_WORK, &cx->i_flags))
+ queue_work(cx->work_queue, &cx->work);
- return (hw2 | sw1 | sw2) ? IRQ_HANDLED : IRQ_NONE;
+ return (sw1 || sw2 || hw2) ? IRQ_HANDLED : IRQ_NONE;
}