diff options
Diffstat (limited to 'drivers/staging/ccree/cc_hw_queue_defs.h')
-rw-r--r-- | drivers/staging/ccree/cc_hw_queue_defs.h | 896 |
1 files changed, 443 insertions, 453 deletions
diff --git a/drivers/staging/ccree/cc_hw_queue_defs.h b/drivers/staging/ccree/cc_hw_queue_defs.h index fbaf1b6fcd90..e6b8cea3f88d 100644 --- a/drivers/staging/ccree/cc_hw_queue_defs.h +++ b/drivers/staging/ccree/cc_hw_queue_defs.h @@ -1,15 +1,15 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ @@ -17,63 +17,95 @@ #ifndef __CC_HW_QUEUE_DEFS_H__ #define __CC_HW_QUEUE_DEFS_H__ -#include "cc_pal_log.h" -#include "cc_regs.h" -#include "dx_crys_kernel.h" - -#ifdef __KERNEL__ #include <linux/types.h> -#define UINT32_MAX 0xFFFFFFFFL -#define INT32_MAX 0x7FFFFFFFL -#define UINT16_MAX 0xFFFFL -#else -#include <stdint.h> -#endif - -/****************************************************************************** -* DEFINITIONS -******************************************************************************/ +#include "dx_crys_kernel.h" +#include <linux/bitfield.h> -/* Dma AXI Secure bit */ -#define AXI_SECURE 0 -#define AXI_NOT_SECURE 1 +/****************************************************************************** + * DEFINITIONS + ******************************************************************************/ #define HW_DESC_SIZE_WORDS 6 #define HW_QUEUE_SLOTS_MAX 15 /* Max. available slots in HW queue */ -#define _HW_DESC_MONITOR_KICK 0x7FFFC00 +#define CC_REG_NAME(word, name) DX_DSCRPTR_QUEUE_WORD ## word ## _ ## name + +#define CC_REG_LOW(word, name) \ + (DX_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SHIFT) + +#define CC_REG_HIGH(word, name) \ + (CC_REG_LOW(word, name) + \ + DX_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SIZE - 1) + +#define CC_GENMASK(word, name) \ + GENMASK(CC_REG_HIGH(word, name), CC_REG_LOW(word, name)) + +#define WORD0_VALUE CC_GENMASK(0, VALUE) +#define WORD1_DIN_CONST_VALUE CC_GENMASK(1, DIN_CONST_VALUE) +#define WORD1_DIN_DMA_MODE CC_GENMASK(1, DIN_DMA_MODE) +#define WORD1_DIN_SIZE CC_GENMASK(1, DIN_SIZE) +#define WORD1_NOT_LAST CC_GENMASK(1, NOT_LAST) +#define WORD1_NS_BIT CC_GENMASK(1, NS_BIT) +#define WORD2_VALUE CC_GENMASK(2, VALUE) +#define WORD3_DOUT_DMA_MODE CC_GENMASK(3, DOUT_DMA_MODE) +#define WORD3_DOUT_LAST_IND CC_GENMASK(3, DOUT_LAST_IND) +#define WORD3_DOUT_SIZE CC_GENMASK(3, DOUT_SIZE) +#define WORD3_HASH_XOR_BIT CC_GENMASK(3, HASH_XOR_BIT) +#define WORD3_NS_BIT CC_GENMASK(3, NS_BIT) +#define WORD3_QUEUE_LAST_IND CC_GENMASK(3, QUEUE_LAST_IND) +#define WORD4_ACK_NEEDED CC_GENMASK(4, ACK_NEEDED) +#define WORD4_AES_SEL_N_HASH CC_GENMASK(4, AES_SEL_N_HASH) +#define WORD4_BYTES_SWAP CC_GENMASK(4, BYTES_SWAP) +#define WORD4_CIPHER_CONF0 CC_GENMASK(4, CIPHER_CONF0) +#define WORD4_CIPHER_CONF1 CC_GENMASK(4, CIPHER_CONF1) +#define WORD4_CIPHER_CONF2 CC_GENMASK(4, CIPHER_CONF2) +#define WORD4_CIPHER_DO CC_GENMASK(4, CIPHER_DO) +#define WORD4_CIPHER_MODE CC_GENMASK(4, CIPHER_MODE) +#define WORD4_CMAC_SIZE0 CC_GENMASK(4, CMAC_SIZE0) +#define WORD4_DATA_FLOW_MODE CC_GENMASK(4, DATA_FLOW_MODE) +#define WORD4_KEY_SIZE CC_GENMASK(4, KEY_SIZE) +#define WORD4_SETUP_OPERATION CC_GENMASK(4, SETUP_OPERATION) +#define WORD5_DIN_ADDR_HIGH CC_GENMASK(5, DIN_ADDR_HIGH) +#define WORD5_DOUT_ADDR_HIGH CC_GENMASK(5, DOUT_ADDR_HIGH) /****************************************************************************** -* TYPE DEFINITIONS -******************************************************************************/ + * TYPE DEFINITIONS + ******************************************************************************/ + +struct cc_hw_desc { + union { + u32 word[HW_DESC_SIZE_WORDS]; + u16 hword[HW_DESC_SIZE_WORDS * 2]; + }; +}; -typedef struct HwDesc { - uint32_t word[HW_DESC_SIZE_WORDS]; -} HwDesc_s; +enum cc_axi_sec { + AXI_SECURE = 0, + AXI_NOT_SECURE = 1 +}; -typedef enum DescDirection { +enum cc_desc_direction { DESC_DIRECTION_ILLEGAL = -1, DESC_DIRECTION_ENCRYPT_ENCRYPT = 0, DESC_DIRECTION_DECRYPT_DECRYPT = 1, DESC_DIRECTION_DECRYPT_ENCRYPT = 3, - DESC_DIRECTION_END = INT32_MAX, -}DescDirection_t; + DESC_DIRECTION_END = S32_MAX, +}; -typedef enum DmaMode { +enum cc_dma_mode { DMA_MODE_NULL = -1, - NO_DMA = 0, + NO_DMA = 0, DMA_SRAM = 1, DMA_DLLI = 2, DMA_MLLI = 3, - DmaMode_OPTIONTS, - DmaMode_END = INT32_MAX, -}DmaMode_t; + DMA_MODE_END = S32_MAX, +}; -typedef enum FlowMode { +enum cc_flow_mode { FLOW_MODE_NULL = -1, /* data flows */ - BYPASS = 0, + BYPASS = 0, DIN_AES_DOUT = 1, AES_to_HASH = 2, AES_and_HASH = 3, @@ -93,11 +125,11 @@ typedef enum FlowMode { DIN_AES_AESMAC = 17, HASH_to_DOUT = 18, /* setup flows */ - S_DIN_to_AES = 32, + S_DIN_to_AES = 32, S_DIN_to_AES2 = 33, S_DIN_to_DES = 34, S_DIN_to_RC4 = 35, - S_DIN_to_MULTI2 = 36, + S_DIN_to_MULTI2 = 36, S_DIN_to_HASH = 37, S_AES_to_DOUT = 38, S_AES2_to_DOUT = 39, @@ -105,47 +137,43 @@ typedef enum FlowMode { S_DES_to_DOUT = 42, S_HASH_to_DOUT = 43, SET_FLOW_ID = 44, - FlowMode_OPTIONTS, - FlowMode_END = INT32_MAX, -}FlowMode_t; + FLOW_MODE_END = S32_MAX, +}; -typedef enum TunnelOp { +enum cc_tunnel_op { TUNNEL_OP_INVALID = -1, TUNNEL_OFF = 0, TUNNEL_ON = 1, - TunnelOp_OPTIONS, - TunnelOp_END = INT32_MAX, -} TunnelOp_t; + TUNNEL_OP_END = S32_MAX, +}; -typedef enum SetupOp { +enum cc_setup_op { SETUP_LOAD_NOP = 0, SETUP_LOAD_STATE0 = 1, SETUP_LOAD_STATE1 = 2, SETUP_LOAD_STATE2 = 3, SETUP_LOAD_KEY0 = 4, SETUP_LOAD_XEX_KEY = 5, - SETUP_WRITE_STATE0 = 8, + SETUP_WRITE_STATE0 = 8, SETUP_WRITE_STATE1 = 9, SETUP_WRITE_STATE2 = 10, SETUP_WRITE_STATE3 = 11, - setupOp_OPTIONTS, - setupOp_END = INT32_MAX, -}SetupOp_t; + SETUP_OP_END = S32_MAX, +}; -enum AesMacSelector { +enum cc_aes_mac_selector { AES_SK = 1, AES_CMAC_INIT = 2, AES_CMAC_SIZE0 = 3, - AesMacEnd = INT32_MAX, + AES_MAC_END = S32_MAX, }; -#define HW_KEY_MASK_CIPHER_DO 0x3 +#define HW_KEY_MASK_CIPHER_DO 0x3 #define HW_KEY_SHIFT_CIPHER_CFG2 2 - /* HwCryptoKey[1:0] is mapped to cipher_do[1:0] */ /* HwCryptoKey[2:3] is mapped to cipher_config2[1:0] */ -typedef enum HwCryptoKey { +enum cc_hw_crypto_key { USER_KEY = 0, /* 0x0000 */ ROOT_KEY = 1, /* 0x0001 */ PROVISIONING_KEY = 2, /* 0x0010 */ /* ==KCP */ @@ -157,447 +185,409 @@ typedef enum HwCryptoKey { KFDE1_KEY = 9, /* 0x1001 */ KFDE2_KEY = 10, /* 0x1010 */ KFDE3_KEY = 11, /* 0x1011 */ - END_OF_KEYS = INT32_MAX, -}HwCryptoKey_t; + END_OF_KEYS = S32_MAX, +}; -typedef enum HwAesKeySize { +enum cc_hw_aes_key_size { AES_128_KEY = 0, AES_192_KEY = 1, AES_256_KEY = 2, - END_OF_AES_KEYS = INT32_MAX, -}HwAesKeySize_t; + END_OF_AES_KEYS = S32_MAX, +}; -typedef enum HwDesKeySize { +enum cc_hw_des_key_size { DES_ONE_KEY = 0, DES_TWO_KEYS = 1, DES_THREE_KEYS = 2, - END_OF_DES_KEYS = INT32_MAX, -}HwDesKeySize_t; + END_OF_DES_KEYS = S32_MAX, +}; /*****************************/ /* Descriptor packing macros */ /*****************************/ -#define GET_HW_Q_DESC_WORD_IDX(descWordIdx) (CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD ## descWordIdx) ) - -#define HW_DESC_INIT(pDesc) do { \ - (pDesc)->word[0] = 0; \ - (pDesc)->word[1] = 0; \ - (pDesc)->word[2] = 0; \ - (pDesc)->word[3] = 0; \ - (pDesc)->word[4] = 0; \ - (pDesc)->word[5] = 0; \ -} while (0) - -/* HW descriptor debug functions */ -int createDetailedDump(HwDesc_s *pDesc); -void descriptor_log(HwDesc_s *desc); - -#if defined(HW_DESCRIPTOR_LOG) || defined(HW_DESC_DUMP_HOST_BUF) -#define LOG_HW_DESC(pDesc) descriptor_log(pDesc) -#else -#define LOG_HW_DESC(pDesc) -#endif - -#if (CC_PAL_MAX_LOG_LEVEL >= CC_PAL_LOG_LEVEL_TRACE) || defined(OEMFW_LOG) - -#ifdef UART_PRINTF -#define CREATE_DETAILED_DUMP(pDesc) createDetailedDump(pDesc) -#else -#define CREATE_DETAILED_DUMP(pDesc) -#endif - -#define HW_DESC_DUMP(pDesc) do { \ - CC_PAL_LOG_TRACE("\n---------------------------------------------------\n"); \ - CREATE_DETAILED_DUMP(pDesc); \ - CC_PAL_LOG_TRACE("0x%08X, ", (unsigned int)(pDesc)->word[0]); \ - CC_PAL_LOG_TRACE("0x%08X, ", (unsigned int)(pDesc)->word[1]); \ - CC_PAL_LOG_TRACE("0x%08X, ", (unsigned int)(pDesc)->word[2]); \ - CC_PAL_LOG_TRACE("0x%08X, ", (unsigned int)(pDesc)->word[3]); \ - CC_PAL_LOG_TRACE("0x%08X, ", (unsigned int)(pDesc)->word[4]); \ - CC_PAL_LOG_TRACE("0x%08X\n", (unsigned int)(pDesc)->word[5]); \ - CC_PAL_LOG_TRACE("---------------------------------------------------\n\n"); \ -} while (0) - -#else -#define HW_DESC_DUMP(pDesc) do {} while (0) -#endif - - -/*! - * This macro indicates the end of current HW descriptors flow and release the HW engines. - * - * \param pDesc pointer HW descriptor struct - */ -#define HW_DESC_SET_QUEUE_LAST_IND(pDesc) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, QUEUE_LAST_IND, (pDesc)->word[3], 1); \ - } while (0) - -/*! - * This macro signs the end of HW descriptors flow by asking for completion ack, and release the HW engines - * - * \param pDesc pointer HW descriptor struct - */ -#define HW_DESC_SET_ACK_LAST(pDesc) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, QUEUE_LAST_IND, (pDesc)->word[3], 1); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, ACK_NEEDED, (pDesc)->word[4], 1); \ - } while (0) - - -#define MSB64(_addr) (sizeof(_addr) == 4 ? 0 : ((_addr) >> 32)&UINT16_MAX) - -/*! - * This macro sets the DIN field of a HW descriptors - * - * \param pDesc pointer HW descriptor struct - * \param dmaMode The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT - * \param dinAdr DIN address - * \param dinSize Data size in bytes - * \param axiNs AXI secure bit +/* + * Init a HW descriptor struct + * @pdesc: pointer HW descriptor struct */ -#define HW_DESC_SET_DIN_TYPE(pDesc, dmaMode, dinAdr, dinSize, axiNs) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (dinAdr)&UINT32_MAX ); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DIN_ADDR_HIGH, (pDesc)->word[5], MSB64(dinAdr) ); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_DMA_MODE, (pDesc)->word[1], (dmaMode)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_SIZE, (pDesc)->word[1], (dinSize)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, NS_BIT, (pDesc)->word[1], (axiNs)); \ - } while (0) - - -/*! - * This macro sets the DIN field of a HW descriptors to NO DMA mode. Used for NOP descriptor, register patches and - * other special modes - * - * \param pDesc pointer HW descriptor struct - * \param dinAdr DIN address - * \param dinSize Data size in bytes +static inline void hw_desc_init(struct cc_hw_desc *pdesc) +{ + memset(pdesc, 0, sizeof(struct cc_hw_desc)); +} + +/* + * Indicates the end of current HW descriptors flow and release the HW engines. + * + * @pdesc: pointer HW descriptor struct */ -#define HW_DESC_SET_DIN_NO_DMA(pDesc, dinAdr, dinSize) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (uint32_t)(dinAdr)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_SIZE, (pDesc)->word[1], (dinSize)); \ - } while (0) - -/*! - * This macro sets the DIN field of a HW descriptors to SRAM mode. - * Note: No need to check SRAM alignment since host requests do not use SRAM and - * adaptor will enforce alignment check. - * - * \param pDesc pointer HW descriptor struct - * \param dinAdr DIN address - * \param dinSize Data size in bytes +static inline void set_queue_last_ind(struct cc_hw_desc *pdesc) +{ + pdesc->word[3] |= FIELD_PREP(WORD3_QUEUE_LAST_IND, 1); +} + +/* + * Set the DIN field of a HW descriptors + * + * @pdesc: pointer HW descriptor struct + * @dma_mode: dmaMode The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT + * @addr: dinAdr DIN address + * @size: Data size in bytes + * @axi_sec: AXI secure bit */ -#define HW_DESC_SET_DIN_SRAM(pDesc, dinAdr, dinSize) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (uint32_t)(dinAdr)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_DMA_MODE, (pDesc)->word[1], DMA_SRAM); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_SIZE, (pDesc)->word[1], (dinSize)); \ - } while (0) - -/*! This macro sets the DIN field of a HW descriptors to CONST mode - * - * \param pDesc pointer HW descriptor struct - * \param val DIN const value - * \param dinSize Data size in bytes +static inline void set_din_type(struct cc_hw_desc *pdesc, + enum cc_dma_mode dma_mode, dma_addr_t addr, + u32 size, enum cc_axi_sec axi_sec) +{ + pdesc->word[0] = (u32)addr; +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + pdesc->word[5] |= FIELD_PREP(WORD5_DIN_ADDR_HIGH, ((u16)(addr >> 32))); +#endif + pdesc->word[1] |= FIELD_PREP(WORD1_DIN_DMA_MODE, dma_mode) | + FIELD_PREP(WORD1_DIN_SIZE, size) | + FIELD_PREP(WORD1_NS_BIT, axi_sec); +} + +/* + * Set the DIN field of a HW descriptors to NO DMA mode. + * Used for NOP descriptor, register patches and other special modes. + * + * @pdesc: pointer HW descriptor struct + * @addr: DIN address + * @size: Data size in bytes */ -#define HW_DESC_SET_DIN_CONST(pDesc, val, dinSize) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (uint32_t)(val)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_CONST_VALUE, (pDesc)->word[1], 1); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_DMA_MODE, (pDesc)->word[1], DMA_SRAM); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_SIZE, (pDesc)->word[1], (dinSize)); \ - } while (0) - -/*! - * This macro sets the DIN not last input data indicator - * - * \param pDesc pointer HW descriptor struct +static inline void set_din_no_dma(struct cc_hw_desc *pdesc, u32 addr, u32 size) +{ + pdesc->word[0] = addr; + pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size); +} + +/* + * Set the DIN field of a HW descriptors to SRAM mode. + * Note: No need to check SRAM alignment since host requests do not use SRAM and + * adaptor will enforce alignment check. + * + * @pdesc: pointer HW descriptor struct + * @addr: DIN address + * @size Data size in bytes */ -#define HW_DESC_SET_DIN_NOT_LAST_INDICATION(pDesc) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, NOT_LAST, (pDesc)->word[1], 1); \ - } while (0) - -/*! - * This macro sets the DOUT field of a HW descriptors - * - * \param pDesc pointer HW descriptor struct - * \param dmaMode The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT - * \param doutAdr DOUT address - * \param doutSize Data size in bytes - * \param axiNs AXI secure bit +static inline void set_din_sram(struct cc_hw_desc *pdesc, dma_addr_t addr, + u32 size) +{ + pdesc->word[0] = (u32)addr; + pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size) | + FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM); +} + +/* + * Set the DIN field of a HW descriptors to CONST mode + * + * @pdesc: pointer HW descriptor struct + * @val: DIN const value + * @size: Data size in bytes */ -#define HW_DESC_SET_DOUT_TYPE(pDesc, dmaMode, doutAdr, doutSize, axiNs) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr)&UINT32_MAX ); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DOUT_ADDR_HIGH, (pDesc)->word[5], MSB64(doutAdr) ); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], (dmaMode)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, NS_BIT, (pDesc)->word[3], (axiNs)); \ - } while (0) - -/*! - * This macro sets the DOUT field of a HW descriptors to DLLI type - * The LAST INDICATION is provided by the user - * - * \param pDesc pointer HW descriptor struct - * \param doutAdr DOUT address - * \param doutSize Data size in bytes - * \param lastInd The last indication bit - * \param axiNs AXI secure bit +static inline void set_din_const(struct cc_hw_desc *pdesc, u32 val, u32 size) +{ + pdesc->word[0] = val; + pdesc->word[1] |= FIELD_PREP(WORD1_DIN_CONST_VALUE, 1) | + FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM) | + FIELD_PREP(WORD1_DIN_SIZE, size); +} + +/* + * Set the DIN not last input data indicator + * + * @pdesc: pointer HW descriptor struct */ -#define HW_DESC_SET_DOUT_DLLI(pDesc, doutAdr, doutSize, axiNs ,lastInd) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr)&UINT32_MAX ); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DOUT_ADDR_HIGH, (pDesc)->word[5], MSB64(doutAdr) ); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], DMA_DLLI); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_LAST_IND, (pDesc)->word[3], lastInd); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, NS_BIT, (pDesc)->word[3], (axiNs)); \ - } while (0) - -/*! - * This macro sets the DOUT field of a HW descriptors to DLLI type - * The LAST INDICATION is provided by the user - * - * \param pDesc pointer HW descriptor struct - * \param doutAdr DOUT address - * \param doutSize Data size in bytes - * \param lastInd The last indication bit - * \param axiNs AXI secure bit +static inline void set_din_not_last_indication(struct cc_hw_desc *pdesc) +{ + pdesc->word[1] |= FIELD_PREP(WORD1_NOT_LAST, 1); +} + +/* + * Set the DOUT field of a HW descriptors + * + * @pdesc: pointer HW descriptor struct + * @dma_mode: The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT + * @addr: DOUT address + * @size: Data size in bytes + * @axi_sec: AXI secure bit */ -#define HW_DESC_SET_DOUT_MLLI(pDesc, doutAdr, doutSize, axiNs ,lastInd) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr)&UINT32_MAX ); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DOUT_ADDR_HIGH, (pDesc)->word[5], MSB64(doutAdr) ); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], DMA_MLLI); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_LAST_IND, (pDesc)->word[3], lastInd); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, NS_BIT, (pDesc)->word[3], (axiNs)); \ - } while (0) - -/*! - * This macro sets the DOUT field of a HW descriptors to NO DMA mode. Used for NOP descriptor, register patches and - * other special modes - * - * \param pDesc pointer HW descriptor struct - * \param doutAdr DOUT address - * \param doutSize Data size in bytes - * \param registerWriteEnable Enables a write operation to a register +static inline void set_dout_type(struct cc_hw_desc *pdesc, + enum cc_dma_mode dma_mode, dma_addr_t addr, + u32 size, enum cc_axi_sec axi_sec) +{ + pdesc->word[2] = (u32)addr; +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + pdesc->word[5] |= FIELD_PREP(WORD5_DOUT_ADDR_HIGH, ((u16)(addr >> 32))); +#endif + pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, dma_mode) | + FIELD_PREP(WORD3_DOUT_SIZE, size) | + FIELD_PREP(WORD3_NS_BIT, axi_sec); +} + +/* + * Set the DOUT field of a HW descriptors to DLLI type + * The LAST INDICATION is provided by the user + * + * @pdesc pointer HW descriptor struct + * @addr: DOUT address + * @size: Data size in bytes + * @last_ind: The last indication bit + * @axi_sec: AXI secure bit */ -#define HW_DESC_SET_DOUT_NO_DMA(pDesc, doutAdr, doutSize, registerWriteEnable) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(doutAdr)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_LAST_IND, (pDesc)->word[3], (registerWriteEnable)); \ - } while (0) - -/*! - * This macro sets the word for the XOR operation. - * - * \param pDesc pointer HW descriptor struct - * \param xorVal xor data value +static inline void set_dout_dlli(struct cc_hw_desc *pdesc, dma_addr_t addr, + u32 size, enum cc_axi_sec axi_sec, + u32 last_ind) +{ + set_dout_type(pdesc, DMA_DLLI, addr, size, axi_sec); + pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind); +} + +/* + * Set the DOUT field of a HW descriptors to DLLI type + * The LAST INDICATION is provided by the user + * + * @pdesc: pointer HW descriptor struct + * @addr: DOUT address + * @size: Data size in bytes + * @last_ind: The last indication bit + * @axi_sec: AXI secure bit */ -#define HW_DESC_SET_XOR_VAL(pDesc, xorVal) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(xorVal)); \ - } while (0) - -/*! - * This macro sets the XOR indicator bit in the descriptor - * - * \param pDesc pointer HW descriptor struct +static inline void set_dout_mlli(struct cc_hw_desc *pdesc, dma_addr_t addr, + u32 size, enum cc_axi_sec axi_sec, + bool last_ind) +{ + set_dout_type(pdesc, DMA_MLLI, addr, size, axi_sec); + pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind); +} + +/* + * Set the DOUT field of a HW descriptors to NO DMA mode. + * Used for NOP descriptor, register patches and other special modes. + * + * @pdesc: pointer HW descriptor struct + * @addr: DOUT address + * @size: Data size in bytes + * @write_enable: Enables a write operation to a register */ -#define HW_DESC_SET_XOR_ACTIVE(pDesc) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, HASH_XOR_BIT, (pDesc)->word[3], 1); \ - } while (0) - -/*! - * This macro selects the AES engine instead of HASH engine when setting up combined mode with AES XCBC MAC - * - * \param pDesc pointer HW descriptor struct +static inline void set_dout_no_dma(struct cc_hw_desc *pdesc, u32 addr, + u32 size, bool write_enable) +{ + pdesc->word[2] = addr; + pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_SIZE, size) | + FIELD_PREP(WORD3_DOUT_LAST_IND, write_enable); +} + +/* + * Set the word for the XOR operation. + * + * @pdesc: pointer HW descriptor struct + * @val: xor data value */ -#define HW_DESC_SET_AES_NOT_HASH_MODE(pDesc) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, AES_SEL_N_HASH, (pDesc)->word[4], 1); \ - } while (0) - -/*! - * This macro sets the DOUT field of a HW descriptors to SRAM mode - * Note: No need to check SRAM alignment since host requests do not use SRAM and - * adaptor will enforce alignment check. - * - * \param pDesc pointer HW descriptor struct - * \param doutAdr DOUT address - * \param doutSize Data size in bytes +static inline void set_xor_val(struct cc_hw_desc *pdesc, u32 val) +{ + pdesc->word[2] = val; +} + +/* + * Sets the XOR indicator bit in the descriptor + * + * @pdesc: pointer HW descriptor struct */ -#define HW_DESC_SET_DOUT_SRAM(pDesc, doutAdr, doutSize) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(doutAdr)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], DMA_SRAM); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize)); \ - } while (0) - - -/*! - * This macro sets the data unit size for XEX mode in data_out_addr[15:0] - * - * \param pDesc pointer HW descriptor struct - * \param dataUnitSize data unit size for XEX mode +static inline void set_xor_active(struct cc_hw_desc *pdesc) +{ + pdesc->word[3] |= FIELD_PREP(WORD3_HASH_XOR_BIT, 1); +} + +/* + * Select the AES engine instead of HASH engine when setting up combined mode + * with AES XCBC MAC + * + * @pdesc: pointer HW descriptor struct */ -#define HW_DESC_SET_XEX_DATA_UNIT_SIZE(pDesc, dataUnitSize) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(dataUnitSize)); \ - } while (0) +static inline void set_aes_not_hash_mode(struct cc_hw_desc *pdesc) +{ + pdesc->word[4] |= FIELD_PREP(WORD4_AES_SEL_N_HASH, 1); +} -/*! - * This macro sets the number of rounds for Multi2 in data_out_addr[15:0] +/* + * Set the DOUT field of a HW descriptors to SRAM mode + * Note: No need to check SRAM alignment since host requests do not use SRAM and + * adaptor will enforce alignment check. * - * \param pDesc pointer HW descriptor struct - * \param numRounds number of rounds for Multi2 -*/ -#define HW_DESC_SET_MULTI2_NUM_ROUNDS(pDesc, numRounds) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(numRounds)); \ - } while (0) - -/*! - * This macro sets the flow mode. + * @pdesc: pointer HW descriptor struct + * @addr: DOUT address + * @size: Data size in bytes + */ +static inline void set_dout_sram(struct cc_hw_desc *pdesc, u32 addr, u32 size) +{ + pdesc->word[2] = addr; + pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, DMA_SRAM) | + FIELD_PREP(WORD3_DOUT_SIZE, size); +} + +/* + * Sets the data unit size for XEX mode in data_out_addr[15:0] * - * \param pDesc pointer HW descriptor struct - * \param flowMode Any one of the modes defined in [CC7x-DESC] -*/ + * @pdesc: pDesc pointer HW descriptor struct + * @size: data unit size for XEX mode + */ +static inline void set_xex_data_unit_size(struct cc_hw_desc *pdesc, u32 size) +{ + pdesc->word[2] = size; +} -#define HW_DESC_SET_FLOW_MODE(pDesc, flowMode) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, DATA_FLOW_MODE, (pDesc)->word[4], (flowMode)); \ - } while (0) +/* + * Set the number of rounds for Multi2 in data_out_addr[15:0] + * + * @pdesc: pointer HW descriptor struct + * @num: number of rounds for Multi2 + */ +static inline void set_multi2_num_rounds(struct cc_hw_desc *pdesc, u32 num) +{ + pdesc->word[2] = num; +} -/*! - * This macro sets the cipher mode. +/* + * Set the flow mode. * - * \param pDesc pointer HW descriptor struct - * \param cipherMode Any one of the modes defined in [CC7x-DESC] -*/ -#define HW_DESC_SET_CIPHER_MODE(pDesc, cipherMode) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_MODE, (pDesc)->word[4], (cipherMode)); \ - } while (0) - -/*! - * This macro sets the cipher configuration fields. + * @pdesc: pointer HW descriptor struct + * @mode: Any one of the modes defined in [CC7x-DESC] + */ +static inline void set_flow_mode(struct cc_hw_desc *pdesc, + enum cc_flow_mode mode) +{ + pdesc->word[4] |= FIELD_PREP(WORD4_DATA_FLOW_MODE, mode); +} + +/* + * Set the cipher mode. * - * \param pDesc pointer HW descriptor struct - * \param cipherConfig Any one of the modes defined in [CC7x-DESC] -*/ -#define HW_DESC_SET_CIPHER_CONFIG0(pDesc, cipherConfig) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_CONF0, (pDesc)->word[4], (cipherConfig)); \ - } while (0) - -/*! - * This macro sets the cipher configuration fields. + * @pdesc: pointer HW descriptor struct + * @mode: Any one of the modes defined in [CC7x-DESC] + */ +static inline void set_cipher_mode(struct cc_hw_desc *pdesc, + enum drv_cipher_mode mode) +{ + pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_MODE, mode); +} + +/* + * Set the cipher configuration fields. * - * \param pDesc pointer HW descriptor struct - * \param cipherConfig Any one of the modes defined in [CC7x-DESC] -*/ -#define HW_DESC_SET_CIPHER_CONFIG1(pDesc, cipherConfig) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_CONF1, (pDesc)->word[4], (cipherConfig)); \ - } while (0) - -/*! - * This macro sets HW key configuration fields. + * @pdesc: pointer HW descriptor struct + * @mode: Any one of the modes defined in [CC7x-DESC] + */ +static inline void set_cipher_config0(struct cc_hw_desc *pdesc, + enum drv_crypto_direction mode) +{ + pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF0, mode); +} + +/* + * Set the cipher configuration fields. * - * \param pDesc pointer HW descriptor struct - * \param hwKey The hw key number as in enun HwCryptoKey -*/ -#define HW_DESC_SET_HW_CRYPTO_KEY(pDesc, hwKey) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_DO, (pDesc)->word[4], (hwKey)&HW_KEY_MASK_CIPHER_DO); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_CONF2, (pDesc)->word[4], (hwKey>>HW_KEY_SHIFT_CIPHER_CFG2)); \ - } while (0) - -/*! - * This macro changes the bytes order of all setup-finalize descriptosets. + * @pdesc: pointer HW descriptor struct + * @config: Any one of the modes defined in [CC7x-DESC] + */ +static inline void set_cipher_config1(struct cc_hw_desc *pdesc, + enum cc_hash_conf_pad config) +{ + pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF1, config); +} + +/* + * Set HW key configuration fields. * - * \param pDesc pointer HW descriptor struct - * \param swapConfig Any one of the modes defined in [CC7x-DESC] -*/ -#define HW_DESC_SET_BYTES_SWAP(pDesc, swapConfig) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, BYTES_SWAP, (pDesc)->word[4], (swapConfig)); \ - } while (0) - -/*! - * This macro sets the CMAC_SIZE0 mode. + * @pdesc: pointer HW descriptor struct + * @hw_key: The HW key slot asdefined in enum cc_hw_crypto_key + */ +static inline void set_hw_crypto_key(struct cc_hw_desc *pdesc, + enum cc_hw_crypto_key hw_key) +{ + pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO, + (hw_key & HW_KEY_MASK_CIPHER_DO)) | + FIELD_PREP(WORD4_CIPHER_CONF2, + (hw_key >> HW_KEY_SHIFT_CIPHER_CFG2)); +} + +/* + * Set byte order of all setup-finalize descriptors. * - * \param pDesc pointer HW descriptor struct -*/ -#define HW_DESC_SET_CMAC_SIZE0_MODE(pDesc) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CMAC_SIZE0, (pDesc)->word[4], 0x1); \ - } while (0) - -/*! - * This macro sets the key size for AES engine. + * @pdesc: pointer HW descriptor struct + * @config: Any one of the modes defined in [CC7x-DESC] + */ +static inline void set_bytes_swap(struct cc_hw_desc *pdesc, bool config) +{ + pdesc->word[4] |= FIELD_PREP(WORD4_BYTES_SWAP, config); +} + +/* + * Set CMAC_SIZE0 mode. * - * \param pDesc pointer HW descriptor struct - * \param keySize key size in bytes (NOT size code) -*/ -#define HW_DESC_SET_KEY_SIZE_AES(pDesc, keySize) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, KEY_SIZE, (pDesc)->word[4], ((keySize) >> 3) - 2); \ - } while (0) - -/*! - * This macro sets the key size for DES engine. + * @pdesc: pointer HW descriptor struct + */ +static inline void set_cmac_size0_mode(struct cc_hw_desc *pdesc) +{ + pdesc->word[4] |= FIELD_PREP(WORD4_CMAC_SIZE0, 1); +} + +/* + * Set key size descriptor field. * - * \param pDesc pointer HW descriptor struct - * \param keySize key size in bytes (NOT size code) -*/ -#define HW_DESC_SET_KEY_SIZE_DES(pDesc, keySize) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, KEY_SIZE, (pDesc)->word[4], ((keySize) >> 3) - 1); \ - } while (0) - -/*! - * This macro sets the descriptor's setup mode + * @pdesc: pointer HW descriptor struct + * @size: key size in bytes (NOT size code) + */ +static inline void set_key_size(struct cc_hw_desc *pdesc, u32 size) +{ + pdesc->word[4] |= FIELD_PREP(WORD4_KEY_SIZE, size); +} + +/* + * Set AES key size. * - * \param pDesc pointer HW descriptor struct - * \param setupMode Any one of the setup modes defined in [CC7x-DESC] -*/ -#define HW_DESC_SET_SETUP_MODE(pDesc, setupMode) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, SETUP_OPERATION, (pDesc)->word[4], (setupMode)); \ - } while (0) - -/*! - * This macro sets the descriptor's cipher do + * @pdesc: pointer HW descriptor struct + * @size: key size in bytes (NOT size code) + */ +static inline void set_key_size_aes(struct cc_hw_desc *pdesc, u32 size) +{ + set_key_size(pdesc, ((size >> 3) - 2)); +} + +/* + * Set DES key size. * - * \param pDesc pointer HW descriptor struct - * \param cipherDo Any one of the cipher do defined in [CC7x-DESC] -*/ -#define HW_DESC_SET_CIPHER_DO(pDesc, cipherDo) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_DO, (pDesc)->word[4], (cipherDo)&HW_KEY_MASK_CIPHER_DO); \ - } while (0) - -/*! - * This macro sets the DIN field of a HW descriptors to star/stop monitor descriptor. - * Used for performance measurements and debug purposes. - * - * \param pDesc pointer HW descriptor struct + * @pdesc: pointer HW descriptor struct + * @size: key size in bytes (NOT size code) */ -#define HW_DESC_SET_DIN_MONITOR_CNTR(pDesc) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_MEASURE_CNTR, VALUE, (pDesc)->word[1], _HW_DESC_MONITOR_KICK); \ - } while (0) +static inline void set_key_size_des(struct cc_hw_desc *pdesc, u32 size) +{ + set_key_size(pdesc, ((size >> 3) - 1)); +} +/* + * Set the descriptor setup mode + * + * @pdesc: pointer HW descriptor struct + * @mode: Any one of the setup modes defined in [CC7x-DESC] + */ +static inline void set_setup_mode(struct cc_hw_desc *pdesc, + enum cc_setup_op mode) +{ + pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, mode); +} +/* + * Set the descriptor cipher DO + * + * @pdesc: pointer HW descriptor struct + * @config: Any one of the cipher do defined in [CC7x-DESC] + */ +static inline void set_cipher_do(struct cc_hw_desc *pdesc, + enum cc_hash_cipher_pad config) +{ + pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO, + (config & HW_KEY_MASK_CIPHER_DO)); +} #endif /*__CC_HW_QUEUE_DEFS_H__*/ |