diff options
Diffstat (limited to 'drivers/staging/rts5208/rtsx_chip.c')
| -rw-r--r-- | drivers/staging/rts5208/rtsx_chip.c | 607 |
1 files changed, 498 insertions, 109 deletions
diff --git a/drivers/staging/rts5208/rtsx_chip.c b/drivers/staging/rts5208/rtsx_chip.c index a8feee846dd3..0c1716ebc827 100644 --- a/drivers/staging/rts5208/rtsx_chip.c +++ b/drivers/staging/rts5208/rtsx_chip.c @@ -116,22 +116,46 @@ void rtsx_disable_bus_int(struct rtsx_chip *chip) static int rtsx_pre_handle_sdio_old(struct rtsx_chip *chip) { + int retval; + if (chip->ignore_sd && CHK_SDIO_EXIST(chip)) { if (chip->asic_code) { - RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF, - MS_INS_PU | SD_WP_PU | - SD_CD_PU | SD_CMD_PU); + retval = rtsx_write_register(chip, CARD_PULL_CTL5, + 0xFF, + MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU); + if (retval) { + rtsx_trace(chip); + return retval; + } } else { - RTSX_WRITE_REG(chip, FPGA_PULL_CTL, 0xFF, - FPGA_SD_PULL_CTL_EN); + retval = rtsx_write_register(chip, FPGA_PULL_CTL, + 0xFF, + FPGA_SD_PULL_CTL_EN); + if (retval) { + rtsx_trace(chip); + return retval; + } + } + retval = rtsx_write_register(chip, CARD_SHARE_MODE, 0xFF, + CARD_SHARE_48_SD); + if (retval) { + rtsx_trace(chip); + return retval; } - RTSX_WRITE_REG(chip, CARD_SHARE_MODE, 0xFF, CARD_SHARE_48_SD); /* Enable SDIO internal clock */ - RTSX_WRITE_REG(chip, 0xFF2C, 0x01, 0x01); + retval = rtsx_write_register(chip, 0xFF2C, 0x01, 0x01); + if (retval) { + rtsx_trace(chip); + return retval; + } - RTSX_WRITE_REG(chip, SDIO_CTRL, 0xFF, - SDIO_BUS_CTRL | SDIO_CD_CTRL); + retval = rtsx_write_register(chip, SDIO_CTRL, 0xFF, + SDIO_BUS_CTRL | SDIO_CD_CTRL); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->sd_int = 1; chip->sd_io = 1; @@ -151,11 +175,19 @@ static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip) if (chip->driver_first_load) { if (CHECK_PID(chip, 0x5288)) { - RTSX_READ_REG(chip, 0xFE5A, &tmp); + retval = rtsx_read_register(chip, 0xFE5A, &tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } if (tmp & 0x08) sw_bypass_sd = true; } else if (CHECK_PID(chip, 0x5208)) { - RTSX_READ_REG(chip, 0xFE70, &tmp); + retval = rtsx_read_register(chip, 0xFE70, &tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } if (tmp & 0x80) sw_bypass_sd = true; } @@ -173,17 +205,37 @@ static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip) if (sw_bypass_sd) { u8 cd_toggle_mask = 0; - RTSX_READ_REG(chip, TLPTISTAT, &tmp); + retval = rtsx_read_register(chip, TLPTISTAT, &tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } cd_toggle_mask = 0x08; if (tmp & cd_toggle_mask) { /* Disable sdio_bus_auto_switch */ - if (CHECK_PID(chip, 0x5288)) - RTSX_WRITE_REG(chip, 0xFE5A, 0x08, 0x00); - else if (CHECK_PID(chip, 0x5208)) - RTSX_WRITE_REG(chip, 0xFE70, 0x80, 0x00); + if (CHECK_PID(chip, 0x5288)) { + retval = rtsx_write_register(chip, 0xFE5A, + 0x08, 0x00); + if (retval) { + rtsx_trace(chip); + return retval; + } + } else if (CHECK_PID(chip, 0x5208)) { + retval = rtsx_write_register(chip, 0xFE70, + 0x80, 0x00); + if (retval) { + rtsx_trace(chip); + return retval; + } + } - RTSX_WRITE_REG(chip, TLPTISTAT, 0xFF, tmp); + retval = rtsx_write_register(chip, TLPTISTAT, 0xFF, + tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->need_reset |= SD_CARD; } else { @@ -196,8 +248,14 @@ static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip) return STATUS_FAIL; } } else { - RTSX_WRITE_REG(chip, FPGA_PULL_CTL, - FPGA_SD_PULL_CTL_BIT | 0x20, 0); + retval = rtsx_write_register(chip, + FPGA_PULL_CTL, + FPGA_SD_PULL_CTL_BIT | 0x20, + 0); + if (retval) { + rtsx_trace(chip); + return retval; + } } retval = card_share_mode(chip, SD_CARD); if (retval != STATUS_SUCCESS) { @@ -206,16 +264,31 @@ static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip) } /* Enable sdio_bus_auto_switch */ - if (CHECK_PID(chip, 0x5288)) - RTSX_WRITE_REG(chip, 0xFE5A, 0x08, 0x08); - else if (CHECK_PID(chip, 0x5208)) - RTSX_WRITE_REG(chip, 0xFE70, 0x80, 0x80); + if (CHECK_PID(chip, 0x5288)) { + retval = rtsx_write_register(chip, 0xFE5A, + 0x08, 0x08); + if (retval) { + rtsx_trace(chip); + return retval; + } + } else if (CHECK_PID(chip, 0x5208)) { + retval = rtsx_write_register(chip, 0xFE70, + 0x80, 0x80); + if (retval) { + rtsx_trace(chip); + return retval; + } + } chip->chip_insert_with_sdio = 1; chip->sd_io = 1; } } else { - RTSX_WRITE_REG(chip, TLPTISTAT, 0x08, 0x08); + retval = rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->need_reset |= SD_CARD; } @@ -242,8 +315,13 @@ static int rtsx_reset_aspm(struct rtsx_chip *chip) return STATUS_SUCCESS; } - if (CHECK_PID(chip, 0x5208)) - RTSX_WRITE_REG(chip, ASPM_FORCE_CTL, 0xFF, 0x3F); + if (CHECK_PID(chip, 0x5208)) { + ret = rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF, 0x3F); + if (ret) { + rtsx_trace(chip); + return ret; + } + } ret = rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en); if (ret != STATUS_SUCCESS) { rtsx_trace(chip); @@ -276,7 +354,11 @@ static int rtsx_enable_pcie_intr(struct rtsx_chip *chip) } if (chip->phy_debug_mode) { - RTSX_WRITE_REG(chip, CDRESUMECTL, 0x77, 0); + ret = rtsx_write_register(chip, CDRESUMECTL, 0x77, 0); + if (ret) { + rtsx_trace(chip); + return ret; + } rtsx_disable_bus_int(chip); } else { rtsx_enable_bus_int(chip); @@ -327,47 +409,116 @@ int rtsx_reset_chip(struct rtsx_chip *chip) rtsx_disable_aspm(chip); - RTSX_WRITE_REG(chip, HOST_SLEEP_STATE, 0x03, 0x00); + retval = rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 0x00); + if (retval) { + rtsx_trace(chip); + return retval; + } /* Disable card clock */ - RTSX_WRITE_REG(chip, CARD_CLK_EN, 0x1E, 0); + retval = rtsx_write_register(chip, CARD_CLK_EN, 0x1E, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } #ifdef SUPPORT_OCP /* SSC power on, OCD power on */ - if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) - RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, 0); - else - RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, MS_OC_POWER_DOWN); + if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) { + retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } + } else { + retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, + MS_OC_POWER_DOWN); + if (retval) { + rtsx_trace(chip); + return retval; + } + } - RTSX_WRITE_REG(chip, OCPPARA1, OCP_TIME_MASK, OCP_TIME_800); - RTSX_WRITE_REG(chip, OCPPARA2, OCP_THD_MASK, OCP_THD_244_946); - RTSX_WRITE_REG(chip, OCPCTL, 0xFF, CARD_OC_INT_EN | CARD_DETECT_EN); + retval = rtsx_write_register(chip, OCPPARA1, OCP_TIME_MASK, + OCP_TIME_800); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, OCPPARA2, OCP_THD_MASK, + OCP_THD_244_946); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, OCPCTL, 0xFF, + CARD_OC_INT_EN | CARD_DETECT_EN); + if (retval) { + rtsx_trace(chip); + return retval; + } #else /* OC power down */ - RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, OC_POWER_DOWN); + retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, + OC_POWER_DOWN); + if (retval) { + rtsx_trace(chip); + return retval; + } #endif - if (!CHECK_PID(chip, 0x5288)) - RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0xFF, 0x03); + if (!CHECK_PID(chip, 0x5288)) { + retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0xFF, 0x03); + if (retval) { + rtsx_trace(chip); + return retval; + } + } /* Turn off LED */ - RTSX_WRITE_REG(chip, CARD_GPIO, 0xFF, 0x03); + retval = rtsx_write_register(chip, CARD_GPIO, 0xFF, 0x03); + if (retval) { + rtsx_trace(chip); + return retval; + } /* Reset delink mode */ - RTSX_WRITE_REG(chip, CHANGE_LINK_STATE, 0x0A, 0); + retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } /* Card driving select */ - RTSX_WRITE_REG(chip, CARD_DRIVE_SEL, 0xFF, chip->card_drive_sel); + retval = rtsx_write_register(chip, CARD_DRIVE_SEL, 0xFF, + chip->card_drive_sel); + if (retval) { + rtsx_trace(chip); + return retval; + } #ifdef LED_AUTO_BLINK - RTSX_WRITE_REG(chip, CARD_AUTO_BLINK, 0xFF, - LED_BLINK_SPEED | BLINK_EN | LED_GPIO0); + retval = rtsx_write_register(chip, CARD_AUTO_BLINK, 0xFF, + LED_BLINK_SPEED | BLINK_EN | LED_GPIO0); + if (retval) { + rtsx_trace(chip); + return retval; + } #endif if (chip->asic_code) { /* Enable SSC Clock */ - RTSX_WRITE_REG(chip, SSC_CTL1, 0xFF, SSC_8X_EN | SSC_SEL_4M); - RTSX_WRITE_REG(chip, SSC_CTL2, 0xFF, 0x12); + retval = rtsx_write_register(chip, SSC_CTL1, 0xFF, + SSC_8X_EN | SSC_SEL_4M); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, SSC_CTL2, 0xFF, 0x12); + if (retval) { + rtsx_trace(chip); + return retval; + } } /* Disable cd_pwr_save (u_force_rst_core_en=0, u_cd_rst_core_en=0) @@ -377,7 +528,11 @@ int rtsx_reset_chip(struct rtsx_chip *chip) bit[5] u_mac_phy_rst_n_dbg rst_value = 1 bit[4] u_non_sticky_rst_n_dbg rst_value = 0 */ - RTSX_WRITE_REG(chip, CHANGE_LINK_STATE, 0x16, 0x10); + retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x16, 0x10); + if (retval) { + rtsx_trace(chip); + return retval; + } /* Enable ASPM */ if (chip->aspm_l0s_l1_en) { @@ -433,9 +588,18 @@ int rtsx_reset_chip(struct rtsx_chip *chip) } } - RTSX_WRITE_REG(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT); + retval = rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, + LINK_RDY_INT); + if (retval) { + rtsx_trace(chip); + return retval; + } - RTSX_WRITE_REG(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80); + retval = rtsx_write_register(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80); + if (retval) { + rtsx_trace(chip); + return retval; + } retval = rtsx_enable_pcie_intr(chip); if (retval != STATUS_SUCCESS) { @@ -470,8 +634,12 @@ int rtsx_reset_chip(struct rtsx_chip *chip) } else { chip->sd_io = 0; - RTSX_WRITE_REG(chip, SDIO_CTRL, SDIO_BUS_CTRL | SDIO_CD_CTRL, - 0); + retval = rtsx_write_register(chip, SDIO_CTRL, + SDIO_BUS_CTRL | SDIO_CD_CTRL, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } } nextcard: @@ -479,30 +647,68 @@ nextcard: chip->need_reset |= XD_CARD; if (chip->int_reg & MS_EXIST) chip->need_reset |= MS_CARD; - if (chip->int_reg & CARD_EXIST) - RTSX_WRITE_REG(chip, SSC_CTL1, SSC_RSTB, SSC_RSTB); + if (chip->int_reg & CARD_EXIST) { + retval = rtsx_write_register(chip, SSC_CTL1, SSC_RSTB, + SSC_RSTB); + if (retval) { + rtsx_trace(chip); + return retval; + } + } dev_dbg(rtsx_dev(chip), "In %s, chip->need_reset = 0x%x\n", __func__, (unsigned int)(chip->need_reset)); - RTSX_WRITE_REG(chip, RCCTL, 0x01, 0x00); + retval = rtsx_write_register(chip, RCCTL, 0x01, 0x00); + if (retval) { + rtsx_trace(chip); + return retval; + } if (CHECK_PID(chip, 0x5208) || CHECK_PID(chip, 0x5288)) { /* Turn off main power when entering S3/S4 state */ - RTSX_WRITE_REG(chip, MAIN_PWR_OFF_CTL, 0x03, 0x03); + retval = rtsx_write_register(chip, MAIN_PWR_OFF_CTL, 0x03, + 0x03); + if (retval) { + rtsx_trace(chip); + return retval; + } } if (chip->remote_wakeup_en && !chip->auto_delink_en) { - RTSX_WRITE_REG(chip, WAKE_SEL_CTL, 0x07, 0x07); - if (chip->aux_pwr_exist) - RTSX_WRITE_REG(chip, PME_FORCE_CTL, 0xFF, 0x33); + retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x07); + if (retval) { + rtsx_trace(chip); + return retval; + } + if (chip->aux_pwr_exist) { + retval = rtsx_write_register(chip, PME_FORCE_CTL, + 0xFF, 0x33); + if (retval) { + rtsx_trace(chip); + return retval; + } + } } else { - RTSX_WRITE_REG(chip, WAKE_SEL_CTL, 0x07, 0x04); - RTSX_WRITE_REG(chip, PME_FORCE_CTL, 0xFF, 0x30); + retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x04); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, PME_FORCE_CTL, 0xFF, 0x30); + if (retval) { + rtsx_trace(chip); + return retval; + } } - if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) - RTSX_WRITE_REG(chip, PETXCFG, 0x1C, 0x14); + if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) { + retval = rtsx_write_register(chip, PETXCFG, 0x1C, 0x14); + if (retval) { + rtsx_trace(chip); + return retval; + } + } if (chip->asic_code && CHECK_PID(chip, 0x5208)) { retval = rtsx_clr_phy_reg_bit(chip, 0x1C, 2); @@ -513,11 +719,19 @@ nextcard: } if (chip->ft2_fast_mode) { - RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0xFF, - MS_PARTIAL_POWER_ON | SD_PARTIAL_POWER_ON); + retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF, + MS_PARTIAL_POWER_ON | SD_PARTIAL_POWER_ON); + if (retval) { + rtsx_trace(chip); + return retval; + } udelay(chip->pmos_pwr_on_interval); - RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0xFF, - MS_POWER_ON | SD_POWER_ON); + retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF, + MS_POWER_ON | SD_POWER_ON); + if (retval) { + rtsx_trace(chip); + return retval; + } wait_timeout(200); } @@ -570,8 +784,16 @@ static int rts5208_init(struct rtsx_chip *chip) u16 reg = 0; u8 val = 0; - RTSX_WRITE_REG(chip, CLK_SEL, 0x03, 0x03); - RTSX_READ_REG(chip, CLK_SEL, &val); + retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_read_register(chip, CLK_SEL, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->asic_code = val == 0 ? 1 : 0; if (chip->asic_code) { @@ -587,16 +809,28 @@ static int rts5208_init(struct rtsx_chip *chip) chip->phy_debug_mode = reg & PHY_DEBUG_MODE ? 1 : 0; } else { - RTSX_READ_REG(chip, 0xFE80, &val); + retval = rtsx_read_register(chip, 0xFE80, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->ic_version = val; chip->phy_debug_mode = 0; } - RTSX_READ_REG(chip, PDINFO, &val); + retval = rtsx_read_register(chip, PDINFO, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val); chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0; - RTSX_READ_REG(chip, 0xFE50, &val); + retval = rtsx_read_register(chip, 0xFE50, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->hw_bypass_sd = val & 0x01 ? 1 : 0; rtsx_read_config_byte(chip, 0x0E, &val); @@ -606,7 +840,11 @@ static int rts5208_init(struct rtsx_chip *chip) CLR_SDIO_EXIST(chip); if (chip->use_hw_setting) { - RTSX_READ_REG(chip, CHANGE_LINK_STATE, &val); + retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->auto_delink_en = val & 0x80 ? 1 : 0; } @@ -619,22 +857,42 @@ static int rts5288_init(struct rtsx_chip *chip) u8 val = 0, max_func; u32 lval = 0; - RTSX_WRITE_REG(chip, CLK_SEL, 0x03, 0x03); - RTSX_READ_REG(chip, CLK_SEL, &val); + retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_read_register(chip, CLK_SEL, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->asic_code = val == 0 ? 1 : 0; chip->ic_version = 0; chip->phy_debug_mode = 0; - RTSX_READ_REG(chip, PDINFO, &val); + retval = rtsx_read_register(chip, PDINFO, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val); chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0; - RTSX_READ_REG(chip, CARD_SHARE_MODE, &val); + retval = rtsx_read_register(chip, CARD_SHARE_MODE, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } dev_dbg(rtsx_dev(chip), "CARD_SHARE_MODE: 0x%x\n", val); chip->baro_pkg = val & 0x04 ? QFN : LQFP; - RTSX_READ_REG(chip, 0xFE5A, &val); + retval = rtsx_read_register(chip, 0xFE5A, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->hw_bypass_sd = val & 0x10 ? 1 : 0; retval = rtsx_read_cfg_dw(chip, 0, 0x718, &lval); @@ -651,7 +909,11 @@ static int rts5288_init(struct rtsx_chip *chip) CLR_SDIO_EXIST(chip); if (chip->use_hw_setting) { - RTSX_READ_REG(chip, CHANGE_LINK_STATE, &val); + retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->auto_delink_en = val & 0x80 ? 1 : 0; if (CHECK_BARO_PKG(chip, LQFP)) @@ -730,9 +992,17 @@ int rtsx_init_chip(struct rtsx_chip *chip) if ((chip->mmc_ddr_tx_phase > 31) || (chip->mmc_ddr_tx_phase < 0)) chip->mmc_ddr_tx_phase = 0; - RTSX_WRITE_REG(chip, FPDCTL, SSC_POWER_DOWN, 0); + retval = rtsx_write_register(chip, FPDCTL, SSC_POWER_DOWN, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } wait_timeout(200); - RTSX_WRITE_REG(chip, CLK_DIV, 0x07, 0x07); + retval = rtsx_write_register(chip, CLK_DIV, 0x07, 0x07); + if (retval) { + rtsx_trace(chip); + return retval; + } dev_dbg(rtsx_dev(chip), "chip->use_hw_setting = %d\n", chip->use_hw_setting); @@ -1241,13 +1511,19 @@ int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data) int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask, u32 val) { + int retval; u8 mode = 0, tmp; int i; for (i = 0; i < 4; i++) { if (mask & 0xFF) { - RTSX_WRITE_REG(chip, CFGDATA0 + i, - 0xFF, (u8)(val & mask & 0xFF)); + retval = rtsx_write_register(chip, CFGDATA0 + i, + 0xFF, + (u8)(val & mask & 0xFF)); + if (retval) { + rtsx_trace(chip); + return retval; + } mode |= (1 << i); } mask >>= 8; @@ -1255,14 +1531,31 @@ int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask, } if (mode) { - RTSX_WRITE_REG(chip, CFGADDR0, 0xFF, (u8)addr); - RTSX_WRITE_REG(chip, CFGADDR1, 0xFF, (u8)(addr >> 8)); + retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CFGADDR1, 0xFF, + (u8)(addr >> 8)); + if (retval) { + rtsx_trace(chip); + return retval; + } - RTSX_WRITE_REG(chip, CFGRWCTL, 0xFF, - 0x80 | mode | ((func_no & 0x03) << 4)); + retval = rtsx_write_register(chip, CFGRWCTL, 0xFF, + 0x80 | mode | ((func_no & 0x03) << 4)); + if (retval) { + rtsx_trace(chip); + return retval; + } for (i = 0; i < MAX_RW_REG_CNT; i++) { - RTSX_READ_REG(chip, CFGRWCTL, &tmp); + retval = rtsx_read_register(chip, CFGRWCTL, &tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } if ((tmp & 0x80) == 0) break; } @@ -1273,22 +1566,44 @@ int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask, int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val) { + int retval; int i; u8 tmp; u32 data = 0; - RTSX_WRITE_REG(chip, CFGADDR0, 0xFF, (u8)addr); - RTSX_WRITE_REG(chip, CFGADDR1, 0xFF, (u8)(addr >> 8)); - RTSX_WRITE_REG(chip, CFGRWCTL, 0xFF, 0x80 | ((func_no & 0x03) << 4)); + retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CFGADDR1, 0xFF, (u8)(addr >> 8)); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CFGRWCTL, 0xFF, + 0x80 | ((func_no & 0x03) << 4)); + if (retval) { + rtsx_trace(chip); + return retval; + } for (i = 0; i < MAX_RW_REG_CNT; i++) { - RTSX_READ_REG(chip, CFGRWCTL, &tmp); + retval = rtsx_read_register(chip, CFGRWCTL, &tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } if ((tmp & 0x80) == 0) break; } for (i = 0; i < 4; i++) { - RTSX_READ_REG(chip, CFGDATA0 + i, &tmp); + retval = rtsx_read_register(chip, CFGDATA0 + i, &tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } data |= (u32)tmp << (i * 8); } @@ -1415,17 +1730,38 @@ int rtsx_read_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf, int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val) { + int retval; bool finished = false; int i; u8 tmp; - RTSX_WRITE_REG(chip, PHYDATA0, 0xFF, (u8)val); - RTSX_WRITE_REG(chip, PHYDATA1, 0xFF, (u8)(val >> 8)); - RTSX_WRITE_REG(chip, PHYADDR, 0xFF, addr); - RTSX_WRITE_REG(chip, PHYRWCTL, 0xFF, 0x81); + retval = rtsx_write_register(chip, PHYDATA0, 0xFF, (u8)val); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, PHYDATA1, 0xFF, (u8)(val >> 8)); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x81); + if (retval) { + rtsx_trace(chip); + return retval; + } for (i = 0; i < 100000; i++) { - RTSX_READ_REG(chip, PHYRWCTL, &tmp); + retval = rtsx_read_register(chip, PHYRWCTL, &tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } if (!(tmp & 0x80)) { finished = true; break; @@ -1442,16 +1778,29 @@ int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val) int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val) { + int retval; bool finished = false; int i; u16 data = 0; u8 tmp; - RTSX_WRITE_REG(chip, PHYADDR, 0xFF, addr); - RTSX_WRITE_REG(chip, PHYRWCTL, 0xFF, 0x80); + retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x80); + if (retval) { + rtsx_trace(chip); + return retval; + } for (i = 0; i < 100000; i++) { - RTSX_READ_REG(chip, PHYRWCTL, &tmp); + retval = rtsx_read_register(chip, PHYRWCTL, &tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } if (!(tmp & 0x80)) { finished = true; break; @@ -1463,9 +1812,17 @@ int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val) return STATUS_FAIL; } - RTSX_READ_REG(chip, PHYDATA0, &tmp); + retval = rtsx_read_register(chip, PHYDATA0, &tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } data = tmp; - RTSX_READ_REG(chip, PHYDATA1, &tmp); + retval = rtsx_read_register(chip, PHYDATA1, &tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } data |= (u16)tmp << 8; if (val) @@ -1476,13 +1833,22 @@ int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val) int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val) { + int retval; int i; u8 data = 0; - RTSX_WRITE_REG(chip, EFUSE_CTRL, 0xFF, 0x80|addr); + retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF, 0x80 | addr); + if (retval) { + rtsx_trace(chip); + return retval; + } for (i = 0; i < 100; i++) { - RTSX_READ_REG(chip, EFUSE_CTRL, &data); + retval = rtsx_read_register(chip, EFUSE_CTRL, &data); + if (retval) { + rtsx_trace(chip); + return retval; + } if (!(data & 0x80)) break; udelay(1); @@ -1493,7 +1859,11 @@ int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val) return STATUS_TIMEDOUT; } - RTSX_READ_REG(chip, EFUSE_DATA, &data); + retval = rtsx_read_register(chip, EFUSE_DATA, &data); + if (retval) { + rtsx_trace(chip); + return retval; + } if (val) *val = data; @@ -1502,6 +1872,7 @@ int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val) int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val) { + int retval; int i, j; u8 data = 0, tmp = 0xFF; @@ -1512,11 +1883,24 @@ int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val) tmp &= (~(u8)(1 << i)); dev_dbg(rtsx_dev(chip), "Write 0x%x to 0x%x\n", tmp, addr); - RTSX_WRITE_REG(chip, EFUSE_DATA, 0xFF, tmp); - RTSX_WRITE_REG(chip, EFUSE_CTRL, 0xFF, 0xA0|addr); + retval = rtsx_write_register(chip, EFUSE_DATA, 0xFF, tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF, + 0xA0 | addr); + if (retval) { + rtsx_trace(chip); + return retval; + } for (j = 0; j < 100; j++) { - RTSX_READ_REG(chip, EFUSE_CTRL, &data); + retval = rtsx_read_register(chip, EFUSE_CTRL, &data); + if (retval) { + rtsx_trace(chip); + return retval; + } if (!(data & 0x80)) break; wait_timeout(3); @@ -1581,9 +1965,14 @@ int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit) int rtsx_check_link_ready(struct rtsx_chip *chip) { + int retval; u8 val; - RTSX_READ_REG(chip, IRQSTAT0, &val); + retval = rtsx_read_register(chip, IRQSTAT0, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } dev_dbg(rtsx_dev(chip), "IRQSTAT0: 0x%x\n", val); if (val & LINK_RDY_INT) { |