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* clk: mvebu: Expand mv98dx3236-core-clock supportChris Packham2017-02-103-14/+181
* clk: zte: add i2s clocks for zx296718Baoyou Xie2017-02-101-0/+4
* clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR()Wei Yongjun2017-02-071-1/+1
* clk: sunxi-ng: select SUNXI_CCU_MULT for sun5iArnd Bergmann2017-02-061-0/+1
* clk: sunxi-ng: Check kzalloc() for errors and cleanup error pathStephen Boyd2017-02-061-0/+15
* clk: tegra: Add BPMP clock driverThierry Reding2017-02-033-0/+625
* Merge tag 'v4.11-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/...Stephen Boyd2017-02-033-9/+17
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| * clk: rockchip: rk3288: make all niu clocks criticalJacob Chen2017-01-231-7/+14
| * clk: rockchip: use rk3288 vip_out clock idsJacob Chen2017-01-221-1/+1
| * Merge branch 'v4.11-shared/clkids' into v4.11-clk/nextHeiko Stuebner2017-01-221-0/+1
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| | * clk: rockchip: add rk3288 vip_out clock idJacob Chen2017-01-221-0/+1
| * | clk: rockchip: fix the incorrect pclk_edp div width for RK3399Xing Zheng2017-01-181-1/+1
* | | clk: uniphier: add eMMC clock for LD11 and LD20 SoCsMasahiro Yamada2017-02-031-0/+7
* | | clk: uniphier: add NAND clock for all UniPhier SoCsMasahiro Yamada2017-02-031-0/+14
* | | Merge tag 'sunxi-clk-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel...Stephen Boyd2017-02-0346-1332/+4877
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| * | | ARM: dts: sun9i: Switch to new clock bindingsChen-Yu Tsai2017-01-301-297/+107Star
| * | | clk: sunxi-ng: Add A80 Display Engine CCUChen-Yu Tsai2017-01-306-0/+483
| * | | clk: sunxi-ng: Add A80 USB CCUChen-Yu Tsai2017-01-306-0/+309
| * | | clk: sunxi-ng: Add A80 CCUChen-Yu Tsai2017-01-307-0/+1556
| * | | clk: sunxi-ng: Support separately grouped PLL lock status registerChen-Yu Tsai2017-01-302-2/+9
| * | | clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENTChen-Yu Tsai2017-01-301-1/+12
| * | | clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flagChen-Yu Tsai2017-01-301-0/+15
| * | | clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividersChen-Yu Tsai2017-01-301-3/+4
| * | | clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPUMaxime Ripard2017-01-271-1/+1
| * | | clk: sunxi-ng: Call divider_round_rate if we only have a single parentMaxime Ripard2017-01-271-0/+12
| * | | ARM: gr8: Convert to CCUMaxime Ripard2017-01-231-464/+56Star
| * | | ARM: sun5i: Convert to CCUMaxime Ripard2017-01-234-513/+75Star
| * | | clk: sunxi-ng: Add sun5i CCU driverMaxime Ripard2017-01-236-0/+1235
| * | | clk: sunxi-ng: Implement global pre-dividerMaxime Ripard2017-01-232-1/+9
| * | | clk: sunxi-ng: Implement multiplier maximumMaxime Ripard2017-01-236-20/+32
| * | | clk: sunxi-ng: mult: Fix minimum in round rateMaxime Ripard2017-01-231-1/+1
| * | | clk: sunxi-ng: Implement factors offsetsMaxime Ripard2017-01-238-29/+79
| * | | clk: sunxi-ng: multiplier: Add fractional supportMaxime Ripard2017-01-232-0/+10
| * | | clk: sunxi-ng: add support for V3s CCUIcenowy Zheng2017-01-206-0/+851
| * | | dt-bindings: add device binding for the CCU of Allwinner V3sIcenowy Zheng2017-01-201-0/+1
| * | | clk: sunxi-ng: a33: Add CLK_SET_RATE_PARENT to ac-digMylène Josserand2017-01-171-1/+1
| * | | clk: sunxi-ng: A31: Fix spdif clock registerMarcus Cooper2017-01-021-2/+2
| * | | clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33Icenowy Zheng2017-01-021-1/+1
| * | | clk: sunxi-ng: fix PLL_CPUX adjusting on A33Icenowy Zheng2017-01-021-0/+10
| * | | clk: sunxi-ng: fix PLL_CPUX adjusting on H3Ondrej Jirman2017-01-021-0/+10
* | | | clk: qcom: SDHCI enablement on Nexus 5X / 6PJeremy McNicoll2017-01-271-0/+18
* | | | dt-bindings: qcom: clk: Add missing binding for SDCHI enablement on Nexus 5X/6PJeremy McNicoll2017-01-271-0/+1
* | | | Merge tag 'clk-v4.11-samsung-2' of git://linuxtv.org/snawrocki/samsung into c...Stephen Boyd2017-01-277-32/+70
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| * | | | clk: samsung: mark s3c...._clk_sleep_init() as __initMartin Kaiser2017-01-274-8/+8
| * | | | clk: samsung: Add enable/disable support for PLL35XX clocksMarek Szyprowski2017-01-271-7/+38
| * | | | clk: samsung: exynos5433: Correct typos in SoC nameMarek Szyprowski2017-01-271-14/+14
| * | | | clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL ratesMarek Szyprowski2017-01-271-0/+2
| * | | | clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocksMarek Szyprowski2017-01-272-3/+8
* | | | | Merge tag 'clk-renesas-for-v4.11-tag2' of git://git.kernel.org/pub/scm/linux/...Stephen Boyd2017-01-275-18/+150
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| * | | | | clk: renesas: r8a7796: Add IIC-DVFS clockKhiem Nguyen2017-01-271-0/+1
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-03 09:25:15 +0200