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* MIPS: Octeon: Add DTS for D-Link DSR-1000NAaro Koskinen2016-05-133-202/+312
| | | | | | | | | | | | | | | | Add DTS for D-Link DSR-1000N that is usable as is without any "pruning" with APPENDED_DTB. Split out the common parts from octeon_3xxx.dts into octeon_3xxx.dtsi. Compared to builtin generic DTB, we can specificy fixed links properly and avoid probing non-existent I2C devices. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12840/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: panic immediately when panic_on_oopsAaro Koskinen2016-05-131-4/+1Star
| | | | | | | | | | | | | | | | | MIPS wants to sleep 5 seconds before panicking when panic_on_oops is set, with no apparent reason. Remove this feature, since some users may want their systems to fail as quickly as possible. Users who want to delay reboot after panic can use PANIC_TIMEOUT. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: James E.J. Bottomley <jejb@parisc-linux.org> Cc: Helge Deller <deller@gmx.de> Cc: linux-mips@linux-mips.org Cc: linux-parisc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12845/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM47xx: Move SPROM driver to drivers/firmware/Rafał Miłecki2016-05-138-12/+59
| | | | | | | | | | | | | | | | | Broadcom ARM home routers store SPROM content in NVRAM just like MIPS ones. To share SPROM code we need to move it out of arch/mips/ to some common place. We already have bcm47xx_nvram in firmware path and SPROM should fit there as well. This driver is responsible for parsing SoC configuration data into a struct shared between ssb and bcma buses. This was tested with BCM4706 & BCM5357C0 (BCM47XX) and BCM4708A0 (ARCH_BCM_5301X). Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Cc: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12210/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: Make reset_control_ops constPhilipp Zabel2016-05-131-1/+1
| | | | | | | | | | | The reset_ops structure is never modified. Make it const. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Cc: kernel@pengutronix.de Patchwork: https://patchwork.linux-mips.org/patch/12618/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: lantiq: Make reset_control_ops constPhilipp Zabel2016-05-131-1/+1
| | | | | | | | | | | The reset_ops structure is never modified. Make it const. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Cc: kernel@pengutronix.de Patchwork: https://patchwork.linux-mips.org/patch/12619/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: device_tree_init: fill mac addresses when using appended dtbAaro Koskinen2016-05-131-1/+7
| | | | | | | | | | Fill MAC addresses from bootinfo when using appended DTB. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12590/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: device_tree_init: don't fill mac if already setAaro Koskinen2016-05-131-0/+8
| | | | | | | | | | | Don't fill MAC address if it's already set. This allows DTB to override the bootinfo. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12589/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: device_tree_init: use separate pass to fill mac addressesAaro Koskinen2016-05-132-16/+72
| | | | | | | | | | | Use separate pass to fill MAC addresses. This is needed because we want to do this also for the appended DTB. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12588/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Use model string from DTB for unknown board typeAaro Koskinen2016-05-131-2/+10
| | | | | | | | | | | | | Use model string from DTB for board type if the board is unknown. This is more informative, e.g. with EdgeRouter Pro the /proc/cpuinfo will display "ubnt,e200 (CN6120p1.1-1000-NSP)" instead of misleading "Unsupported Board". Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12582/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Initialize system type string after device tree init.Aaro Koskinen2016-05-131-4/+2Star
| | | | | | | | | | Initialize system type string after device tree init. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12583/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: board_type_to_string: return NULL for unsupported boardAaro Koskinen2016-05-132-3/+8
| | | | | | | | | | Return NULL for unsupported board. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12581/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Simplify code in octeon_irq_ciu_gpio_set_type()David Daney2016-05-131-1/+1
| | | | | | | | | | | Use the trigger type passed in to the function instead of reading it back out of the irq_data. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12501/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Add SMP support for OCTEON cn78xx et al.David Daney2016-05-133-16/+139
| | | | | | | | | | | | | | OCTEON chips with the CIU3 interrupt controller use a different IPI mechanism that previous models. Add plat_smp_ops for the cn78xx and probing code to choose between the two types of ops. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12499/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Add support for OCTEON III interrupt controller.David Daney2016-05-133-1/+695
| | | | | | | | | | | | | | | | | | | | | | Add irq_chip support for both IPI and "normal" interrupts of the CIU3 controller. Document the device tree binding for the CIU3. Some functions are non-static as they will be used by follow-on support for MSI-X. Signed-off-by: David Daney <david.daney@cavium.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: devicetree@vger.kernel.org Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12500/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Don't attempt to use nonexistent registers on OCTEON III models.David Daney2016-05-132-17/+30
| | | | | | | | | | | Attempts to read the nonexistent registers results in bus errors. Either use registers that exist, or don't do the access as appropriate. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12502/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Add model checking support for cn73xx, cnf75xx and cn78xxDavid Daney2016-05-134-8/+125
| | | | | | | | | | Follow on patchs need to be able to distinguish the new models. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12498/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Add register definitions for cn73xx, cnf75xx and cn78xx.David Daney2016-05-133-16/+748
| | | | | | | | | | | These new members of the OCTEON III family have some new registers, update some of the definitions for use in follow on patches. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12497/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Select CONFIG_HANDLE_DOMAIN_IRQ and make it work.David Daney2016-05-132-0/+11
| | | | | | | | | | | Per the subject, always select HANDLE_DOMAIN_IRQ, and implement set_irq_regs() so that it actually works. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12496/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Remove some code limiting NR_IRQS to 255David Daney2016-05-131-25/+2Star
| | | | | | | | | | | | | | | Follow-on patches for OCTEON III will increase the number of irqs to potentially more than 256. Increase the width of the octeon_irq_ciu_to_irq to int to be able to handle this case. Remove the hacky code that verified that u8 would not be overflowed. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12495/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Extend number of supported CPUs past 32David Daney2016-05-135-8/+125
| | | | | | | | | | | | To support more than 48 CPUs, the bootinfo structure grows a new coremask structure. Add the definition of the structure and add it to struct cvmx_bootinfo. In prom_init(), copy the new coremask data into the sysinfo structure, and use it in smp_setup(). Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12319/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Remove dead code from cvmx-sysinfo.David Daney2016-05-132-97/+5Star
| | | | | | | | | Get rid of the long unused code. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12318/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add CPU identifiers and probing for Cavium CN73xx and CNF75xx processors.David Daney2016-05-132-0/+4
| | | | | | | | | | Add new processor identifiers for Cavium CN73xx and CNF75xx processors, and probe for them in cpu-probe.c Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12311/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: highmem: Turn flush_cache_kmaps into a no-op.Ralf Baechle2016-05-131-1/+3
| | | | | | | | | | | | It was calling flush_cache_all() which is a no-op since a long time anyway and which was overkill in the old days when it was actually doing something because only the D-cache needs to be flushed, never the I-cache, never the S-cache. Since however highmem on MIPS is still only supported on processors that don't suffer from cache aliases, we could turn flush_cache_kmaps() into a no-op - but for paranoia's sake we rather make it BUG_ON(cpu_has_dc_aliases()). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson64: Remove call to flush_cache_all().Ralf Baechle2016-05-131-1/+0Star
| | | | | | flush_cache_all() is a nop and loongson 3 is fully coherent. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: VR41xx: Use __flush_cache_all instead of flush_cache_all.Ralf Baechle2016-05-131-1/+1
| | | | | | | It's probably a good idea to flush caches before reset and by the time this code was written flush_cache_all did actually still do something. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: MSP71xx: Use __flush_cache_all instead of flush_cache_all.Ralf Baechle2016-05-131-1/+1
| | | | | | | Flushing caches is probably sensible on reset but flush_cache_all has been a no-op for a very long time. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Use __flush_cache_all instead of flush_cache_all.Ralf Baechle2016-05-131-1/+1
| | | | | | flush_cache_all will go away. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath79: Use the reset controller to restart OF machinesAlban Bedel2016-05-131-3/+4
| | | | | | | | | | | | | | Don't set _machine_restart() on OF machines as the reset driver now provides a system restart handler. Signed-off-by: Alban Bedel <albeu@free.fr> Cc: Felix Fietkau <nbd@openwrt.org> Cc: Antony Pavlov <antonynpavlov@gmail.com> Cc: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12235/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath79: Add zboot debug serial supportAlban Bedel2016-05-132-1/+6
| | | | | | | | | | | | | | | Reuse the early printk code to support the serial in zboot. We copy early_printk.c instead of referencing it because we need to build a different object file for the normal kernel and zboot. Signed-off-by: Alban Bedel <albeu@free.fr> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Alex Smith <alex.smith@imgtec.com> Cc: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12234/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath79: Remove the builtin DTB supportAlban Bedel2016-05-133-19/+0Star
| | | | | | | | | | | | | Now that appended DTB is usable we can drop the builtin DTB support. Signed-off-by: Alban Bedel <albeu@free.fr> Cc: Felix Fietkau <nbd@openwrt.org> Cc: Antony Pavlov <antonynpavlov@gmail.com> Cc: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12231/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath79: Add support for DTB passed using the UHI boot protocolAlban Bedel2016-05-131-0/+2
| | | | | | | | | | | | | | This is needed for bootloader supporting UHI and to support appended DTB. Signed-off-by: Alban Bedel <albeu@free.fr> Cc: Felix Fietkau <nbd@openwrt.org> Cc: Antony Pavlov <antonynpavlov@gmail.com> Cc: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12230/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Fix CP0_EBASE redefinition warningsJames Hogan2016-05-092-9/+6Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | A couple of netlogic assembly files define CP0_EBASE to $15, the same as CP0_PRID in mipsregs.h, and use it for accessing both CP0_PRId and CP0_EBase registers. However commit 609cf6f2291a ("MIPS: CPS: Early debug using an ns16550-compatible UART") added a different definition of CP0_EBASE to mipsregs.h, which included a register select of 1. This causes harmless build warnings like the following: arch/mips/netlogic/common/reset.S:53:0: warning: "CP0_EBASE" redefined #define CP0_EBASE $15 ^ In file included from arch/mips/netlogic/common/reset.S:41:0: ./arch/mips/include/asm/mipsregs.h:63:0: note: this is the location of the previous definition #define CP0_EBASE $15, 1 ^ Update the code to use the definitions from mipsregs.h for accessing both registers. Fixes: 609cf6f2291a ("MIPS: CPS: Early debug using an ns16550-compatible UART") Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13183/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Adjust set_pte() SMP fix to handle R10000_LLSC_WARJoshua Kinard2016-05-091-13/+32
| | | | | | | | | | | | | | | | | Update the recent changes to set_pte() that were added in 46011e6ea392 to handle R10000_LLSC_WAR, and format the assembly to match other areas of the MIPS tree using the same WAR. This also incorporates a patch recently sent in my Markos Chandras, "Remove local LL/SC preprocessor variants", so that patch doesn't need to be applied if this one is accepted. Signed-off-by: Joshua Kinard <kumba@gentoo.org> Fixes: 46011e6ea392 ("MIPS: Make set_pte() SMP safe.) Cc: David Daney <david.daney@cavium.com> Cc: Linux/MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/11103/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Move definitions for 32/64-bit agonstic inline assembler to new file.Ralf Baechle2016-05-093-25/+31
| | | | | | | | Inspired by Markos Chandras' patch. I just didn't want do pull bitsops.h into pgtable.h. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> References: https://patchwork.linux-mips.org/patch/11052/
* MIPS: Fix MSA assembly warningsJames Hogan2016-05-091-0/+6
| | | | | | | | | | | | | | | | | Building an MSA capable kernel with a toolchain that supports MSA produces warnings such as this: arch/mips/kernel/r4k_fpu.S:229: Warning: the `msa' extension requires 64-bit FPRs This is due to ".set msa" without ".set fp=64" in the non doubleword MSA load/store macros, since MSA requires the 64-bit FPU registers (FR=1). Add the missing fp=64 in these macros to silence the warnings. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13063/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix MSA assembly with big thread offsetsJames Hogan2016-05-091-66/+83
| | | | | | | | | | | | | | | | | | | | | | When lockdep is enabled on a 64-bit kernel the FPR offset into the thread structure exceeds the maximum range of the MSA ld.d/st.d instructions. For example THREAD_FPR31 = 4644 (instead of 2448), while the signed immediate field is only 10 bits with an implicit multiply by 8, giving a maximum offset of 511*8 = 4088. This isn't a problem when the toolchain doesn't support MSA as the ld_*/st_* macros perform the addition separately into $1 with [d]addui which has a 16bit signed immediate field. Fix the case where the toolchain does support MSA by doing a single addition of THREAD_FPR0 into $1 with [d]addui, and doing the ld_*/st_* relative to that. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13064/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix MSA ld_*/st_* asm macros to use PTR_ADDUJames Hogan2016-05-091-8/+8
| | | | | | | | | | | | | | The MSA ld_*/st_* assembler macros for when the toolchain doesn't support MSA use addu to offset the base address. However it is a virtual memory pointer so fix it to use PTR_ADDU which expands to daddu for 64-bit kernels. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 4.3.y- Patchwork: https://patchwork.linux-mips.org/patch/13062/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Use copy_s.fmt rather than copy_u.fmtPaul Burton2016-05-092-17/+17
| | | | | | | | | | | | | | | | | | | | In revision 1.12 of the MSA specification, the copy_u.w instruction has been removed for MIPS32 & the copy_u.d instruction has been removed for MIPS64. Newer toolchains (eg. Codescape SDK essentials 2015.10) will complain about this like so: arch/mips/kernel/r4k_fpu.S:290: Error: opcode not supported on this processor: mips32r2 (mips32r2) `copy_u.w $1,$w26[3]' Since we always copy to the width of a GPR, simply use copy_s instead of copy_u to fix this. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 4.3.x+ Patchwork: https://patchwork.linux-mips.org/patch/13061/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: memset.S: Disable code unused with non-R6 MIPS configsMaciej W. Rozycki2016-05-091-0/+2
| | | | | | | | | | This complements commit 8c56208aff77 ("MIPS: lib: memset: Add MIPS R6 support"). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12452/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS64: R6: R2 emulation bugfixLeonid Yegoshin2016-05-091-52/+53
| | | | | | | | | | | | | | | | | | | | Error recovery pointers for fixups was improperly set as ".word" which is unsuitable for MIPS64. Replaced by STR(PTR) [ralf@linux-mips.org: Apply changes as requested in the review process.] Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Fixes: b0a668fb2038 ("MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6") Cc: macro@linux-mips.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: <stable@vger.kernel.org> # 4.0+ Patchwork: https://patchwork.linux-mips.org/patch/9911/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: dma-default: Defend against NULL dev in massage_gfp_flagsMatt Redfearn2016-05-091-3/+4
| | | | | | | | | | | This patch ensures that the dev parameter is checked for NULL before it is dereferenced in massage_gfp_flags. If dev is NULL, then fall back setting the GFP flag requested and available. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11919/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: oprofile: Fix a preemption issueYanjiang Jin2016-05-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use boot_cpu_type() instead of current_cpu_type() in oprofile_arch_init() to avoid the below warning, cpu_type is normally consistent in a MIPS SMP system. There are a few exceptions such as SGI servers where it is possible to mix R10000, R12000, R14000 and R16000 within certain constraints. Let's not worry about those now. BUG: using smp_processor_id() in preemptible [00000000] code: insmod/952 caller is oprofile_arch_init+0x30/0x194 [oprofile] CPU: 5 PID: 952 Comm: insmod Not tainted 4.1.13-WR8.0.0.0_standard #1 Stack : ffffffff80c10000 0000000000000001 8000000025bf0790 ffffffff80e10000 ffffffff80e50000 ffffffff80254e2c ffffffff80b64428 ffffffff80e10790 0000000000000000 ffffffff801caeb8 0000000000000045 0000000000000005 ffffffff80c10000 ffffffff801cb798 0000000000000000 ffffffff80e30000 0000000000000000 ffffffff801ff1c0 ffffffff80e2d2f8 000000000000000b ffffffff801cbba0 ffffffff80e107b0 ffffffff80a77828 0000000000000005 00000000000003b8 ffffffff80e2d2f8 800000040ad39960 ffffffff801f9950 0000000000000124 80000004093b7990 80000004093b7ab8 ffffffff80925108 ffffffff80b69a07 ffffffff80a6f0d0 8000000407240e00 ffffffff801cc934 000000000000005d ffffffff80159080 0000000000000005 00000000000003b8 ... Call Trace: [<ffffffff80159080>] show_stack+0xe8/0x108 [<ffffffff80925108>] dump_stack+0x8c/0xd8 [<ffffffff80606570>] check_preemption_disabled+0x110/0x118 [<ffffffffc0086104>] oprofile_arch_init+0x30/0x194 [oprofile] [<ffffffffc008602c>] oprofile_init+0x2c/0xc0 [oprofile] [<ffffffff80100550>] do_one_initcall+0xa0/0x1c0 [<ffffffff80921e04>] do_init_module+0x80/0x1d8 [<ffffffff801fd0d4>] load_module+0x1b74/0x2278 [<ffffffff801fdab4>] SyS_finit_module+0xcc/0xf0 [<ffffffff80165884>] handle_sysn32+0x44/0x70 [ralf@linux-mips.org: Correct commit message.] Signed-off-by: Yanjiang Jin <yanjiang.jin@windriver.com> Cc: rric@kernel.org Cc: jinyanjiang@gmail.com Cc: linux-mips@linux-mips.org Cc: oprofile-list@lists.sf.net Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11769/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson-3: Fix build error after ld-version.sh modificationHuacai Chen2016-05-091-1/+1
| | | | | | | | | | | | | | | | | Commit d5ece1cb074b2c ("Fix ld-version.sh to handle large 3rd version part") modifies the ld version description. This causes a build error on Loongson-3, so fix it. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12890/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson-3: Reserve 32MB for RS780E integrated GPUHuacai Chen2016-05-091-3/+3
| | | | | | | | | | | | | | | | | Due to datasheet, reserving 0xff800000~0xffffffff (8MB below 4GB) is not enough for RS780E integrated GPU's TOM (top of memory) registers and MSI/MSI-x memory region, so we reserve 0xfe000000~0xffffffff (32MB below 4GB). Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12889/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Reserve nosave data for hibernationHuacai Chen2016-05-091-0/+3
| | | | | | | | | | | | | | | | | | After commit 92923ca3aacef63c92d ("mm: meminit: only set page reserved in the memblock region"), the MIPS hibernation is broken. Because pages in nosave data section should be "reserved", but currently they aren't set to "reserved" at initialization. This patch makes hibernation work again. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12888/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Sibyte: Fix Kconfig dependencies of SIBYTE_BUS_WATCHERAndreas Ruprecht2016-05-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Commit 6793f55cbc84 ("MIPS: sibyte: Amend dependencies for SIBYTE_BUS_WATCHER") changed the dependencies for SIBYTE_BUS_WATCHER to make it visible only if SIBYTE_BCM112X or SIBYTE_SB1250 are enabled. In the code in arch/mips/sibyte/common/bus_watcher, however, a #if defined() check suggests that this functionality should also be available for SIBYTE_BCM1x55 and SIBYTE_BCM1x80. Make it selectable by extending the dependencies of SIBYTE_BUS_WATCHER in arch/mips/sibyte/Kconfig. Reported-by: Jonas Rabenstein <jonas.rabenstein@studium.uni-erlangen.de> Signed-off-by: Andreas Ruprecht <andreas.ruprecht@fau.de> Cc: valentinrothberg@gmail.com Cc: stefan.hengelein@fau.de Cc: pebolle@tiscali.nl Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10736/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: I6400: Icache fills from dcacheJames Hogan2016-05-091-0/+1
| | | | | | | | | | | | | | | | Coherence Manager 3 (CM3) as present in I6400 can fill icache lines effectively from dirty dcaches, so there is no need to flush dirty lines from dcaches through to L2 prior to icache invalidation. Set the MIPS_CACHE_IC_F_DC flag such that cpu_has_ic_fills_f_dc evaluates to true, which avoids those dcache flushes. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: Manuel Lauss <manuel.lauss@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12180/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: c-r4k: Sync icache when it fills from dcacheJames Hogan2016-05-092-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is still necessary to handle icache coherency in flush_cache_range() and copy_to_user_page() when the icache fills from the dcache, even though the dcache does not need to be written back. However when this handling was added in commit 2eaa7ec286db ("[MIPS] Handle I-cache coherency in flush_cache_range()"), it did not do any icache flushing when it fills from dcache. Therefore fix r4k_flush_cache_range() to run local_r4k_flush_cache_range() without taking into account whether icache fills from dcache, so that the icache coherency gets handled. Checks are also added in local_r4k_flush_cache_range() so that the dcache blast doesn't take place when icache fills from dcache. A test to mmap a page PROT_READ|PROT_WRITE, modify code in it, and mprotect it to VM_READ|VM_EXEC (similar to case described in above commit) can hit this case quite easily to verify the fix. A similar check was added in commit f8829caee311 ("[MIPS] Fix aliasing bug in copy_to_user_page / copy_from_user_page"), so also fix copy_to_user_page() similarly, to call flush_cache_page() without taking into account whether icache fills from dcache, since flush_cache_page() already takes that into account to avoid performing a dcache flush. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: Manuel Lauss <manuel.lauss@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12179/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Enable ptrace hw watchpoints on MIPS R6James Hogan2016-05-091-1/+1
| | | | | | | | | | | | | | HARDWARE_WATCHPOINTS isn't being enabled for CPU_MIPSR6, even though it has an identical hardware watchpoint interface to CPU_MIPSR2, which prevents ptrace watchpoints from being loaded when executing a ptraced process even though the watchpoints are described in /proc/cpuinfo. Enable HARDWARE_WATCHPOINTS for CPU_MIPSR6 too. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12727/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix watchpoint restorationJames Hogan2016-05-094-10/+9Star
| | | | | | | | | | | | | | | | | | | | | | | Commit f51246efee2b ("MIPS: Get rid of finish_arch_switch().") moved the __restore_watch() call from finish_arch_switch() (i.e. after resume() returns) to before the resume() call in switch_to(). This results in watchpoints only being restored when a task is descheduled, preventing the watchpoints from being effective most of the time, except due to chance before the watchpoints are lazily removed. Fix the call sequence from switch_to() through to mips_install_watch_registers() to pass the task_struct pointer of the next task, instead of using current. This allows the watchpoints for the next (non-current) task to be restored without reintroducing finish_arch_switch(). Fixes: f51246efee2b ("MIPS: Get rid of finish_arch_switch().") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 4.3.x- Patchwork: https://patchwork.linux-mips.org/patch/12726/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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