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| * | ARM: socfpga: support suspend to ramAlan Tull2015-06-116-3/+305
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add code that requests that the sdr controller go into self-refresh mode. This code is run from ocram. Suspend-to-RAM and EDAC support are mutually exclusive on SOCFPGA. If the EDAC is enabled, it will prevent the platform from going into suspend. Example of how to request to suspend to ram: $ echo enabled > \ /sys/devices/soc/ffc02000.serial0/tty/ttyS0/power/wakeup $ echo -n mem > /sys/power/state Signed-off-by: Alan Tull <atull@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
| * | ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10Dinh Nguyen2015-06-112-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add boot_secondary implementation for the Arria10 platform. Bringing up the secondary core on the Arria 10 platform is pretty similar to the Cyclone/Arria 5 platform, with the exception of the following differences: - Register offset to bringup CPU1 out of reset is different. - The cpu1-start-addr for Arria10 contains an additional nibble. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
| * | ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5Dinh Nguyen2015-06-113-3/+3
| | | | | | | | | | | | | | | | | | | | | Convert cyclone5/arria5 to use CPU_METHOD_OF_DECLARE for smp operations. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
* | | ARM: Kconfig: Select clocksource in STM32 entryMaxime Coquelin2015-06-011-0/+1
| | | | | | | | | | | | | | | | | | | | | STM32 clocksource driver needs to be selected if ARCH_STM32. Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | | Merge tag 'arm-soc/for-4.2/soc-part2' of http://github.com/broadcom/stblinux ↵Arnd Bergmann2015-06-014-4/+16
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/soc Merge "changes for Broadcom SoCs": - Dan fixes an error path in the BCM63xx SMP code - Ray adds the relevant Kconfig selects to enable the Broadcom NAND driver on Cygnus - Kevin provides a change to the Broadcom GISB arbiter driver to make it work with MIPS-based big-endian STB SoCs (this was a long-standing change that had dependencies on code in drivers/of/*) - Gregory enables the use of GPIOLIB for brcmstb SoCs and bumps the number of GPIOs for these platforms * tag 'arm-soc/for-4.2/soc-part2' of http://github.com/broadcom/stblinux: ARM: brcmstb: Add default gpio number ARM: brcmstb: Select ARCH_WANT_OPTIONAL_GPIOLIB bus: brcmstb_gisb: Honor the "big-endian" and "native-endian" DT properties ARM: BCM: Enable NAND support for iProc SoCs ARM: BCM63xx: fix an error path in bcm63xx_pmb_power_on_cpu()
| * | | ARM: brcmstb: Add default gpio numberGregory Fong2015-05-291-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Out of the brcmstb SoCs that I know, BCM3390 has the largest numbers of GPIOs, with its - 320 "peripheral" GPIOs - 5*32 = 160 UPG GPIOs (counting unused lines, which do get counted) - 2*32 = 64 UPG AON GPIOs (counting unused lines) Total: 544 I suspect that the upper limit will only need to be higher in the future, so set it to 1024. Signed-off-by: Gregory Fong <gregory.0xf0@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| * | | ARM: brcmstb: Select ARCH_WANT_OPTIONAL_GPIOLIBGregory Fong2015-05-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Select ARCH_WANT_OPTIONAL_GPIOLIB from BRCMSTB to allow GPIOLIB and GPIO_BRCMSTB to be enabled. Signed-off-by: Gregory Fong <gregory.0xf0@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| * | | bus: brcmstb_gisb: Honor the "big-endian" and "native-endian" DT propertiesKevin Cernekee2015-05-291-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On chips strapped for BE, we'll need to use ioread32be/iowrite32be instead of ioread32/iowrite32. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| * | | ARM: BCM: Enable NAND support for iProc SoCsRay Jui2015-05-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Select CONFIG_MTD_NAND_BRCMNAND for all iProc SoCs Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| * | | ARM: BCM63xx: fix an error path in bcm63xx_pmb_power_on_cpu()Dan Carpenter2015-05-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to unlock and unmap some resourses before returning. Fixes: 3f2a43c98d72 ('ARM: BCM63xx: Add secondary CPU PMB initialization sequence') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* | | | Merge tag 'renesas-soc-for-v4.2' of ↵Arnd Bergmann2015-05-291-2/+2
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Merge "Renesas ARM Based SoC Updates for v4.2" from Simon Horman: * Only select sound drivers that build * tag 'renesas-soc-for-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: only select sound drivers that build
| * | | | ARM: shmobile: only select sound drivers that buildArnd Bergmann2015-05-251-2/+2
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A couple of codec drivers are selected by shmobile platform code, but depend on I2C, which results in a build error: sound/soc/codecs/ak4642.c:638:1: warning: data definition has no type or storage class module_i2c_driver(ak4642_i2c_driver); ^ sound/soc/codecs/ak4642.c:638:1: error: type defaults to 'int' in declaration of 'module_i2c_driver' [-Werror=implicit-int] sound/soc/codecs/ak4642.c:638:1: warning: parameter names (without types) in function declaration sound/soc/codecs/ak4642.c:627:26: warning: 'ak4642_i2c_driver' defined but not used [-Wunused-variable] This ensures that we do not enable the respective drivers when I2C is disabled. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | ARM: use ARM_SINGLE_ARMV7M for ARMv7-M platformsStefan Agner2015-05-223-59/+33Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the new config symbol ARM_SINGLE_ARMV7M which groups config symbols used by modern ARMv7-M platforms. This allows supporting multiple ARMv7-M platforms in one kernel image. However, a common kernel image requires the combined platforms to share the same main memory layout to be bootable. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Joachim Eastwood <manabian@gmail.com> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | | | ARM: zx: fix building with CONFIG_THUMB2_KERNELArnd Bergmann2015-05-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The newly added zx platform causes a build error when CONFIG_THUMB2_KERNEL is enabled: arch/arm/mach-zx/headsmp.S:16: Error: invalid immediate for address calculation (value = 0x00000004) I'm assuming that the ROM code that is calling these entry points runs in ARM mode, so there would be another problem in the same file, and we can solve both problems at once by adding a '.arm' statement that will make zx_resume_jump and zx_secondary_startup both be built as ARM code. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jun Nie <jun.nie@linaro.org> Tested-by: Jun Nie <jun.nie@linaro.org>
* | | | Merge tag 'omap-for-v4.2/omap1-v2' of ↵Arnd Bergmann2015-05-2235-185/+206
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc Merge fixed up omap1 sparse irq support for v4.2 from Tony Lindgren: Add support for CONFIG_SPARSE_IRQ for omap1. This takes us a bit closer to making omap1 support multiarch. After this series we still need to make omap1 use the common clock framework and fix up the drivers to not rely on includes from mach and plat directories. Note that this branch depends on a GPIO driver fix in v4.1-rc3 d2d05c65c40e ("gpio: omap: Fix regression for MPUIO interrupts"). * tag 'omap-for-v4.2/omap1-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP1: Fix section mismatch warnings for omap_cfg_reg ARM: OMAP1: Fix randconfig builds if ARCH_OMAP15XX not selected ARM: OMAP1: Change interrupt numbering for sparse IRQ ARM: omap1: Switch to use MULTI_IRQ ARM: OMAP1: Switch to use generic irqchip in preparation for sparse IRQ ARM: OMAP1: Move UART defines to prepare for sparse IRQ
| * | | | ARM: OMAP1: Fix section mismatch warnings for omap_cfg_regTony Lindgren2015-05-211-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is cleary used after init time too for example for configuring UART wake-up events during runtime. This fixes section mismatch warnings for randconfig builds that happen because __init_or_module. Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | | ARM: OMAP1: Fix randconfig builds if ARCH_OMAP15XX not selectedTony Lindgren2015-05-217-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the omap1 SPARSE_IRQ changes mach/irqs.h is no longer automatically included. Turns out now we rely on ARCH_OMAP15XX including hardware.h from memory.h, so without ARCH_OMAP15XX we get build failures. As we have legacy drivers still relying on these indirect includes, let's not add more mach includes to the drivers. Those have to be removed anyways for multiplatform support. Let's fix up mach-omap1 to include soc.h where cpu_is_omap checks are done, and common.h for board-*.c files. But let's keep the indirect memory.h include for now to avoid unnecessary churn in the drivers. Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | | ARM: OMAP1: Change interrupt numbering for sparse IRQTony Lindgren2015-05-209-71/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change interrupt numbering for sparse IRQ. We do this using a fixed offset until we can drop irqs.h once all it's users have been updated. Note that this depends on the GPIO fix for the MPUIO IRQs "gpio: omap: Fix regression for MPUIO interrupts". Also note that this patch adds some extra irq alloc warnings that will go away when we stop calling irq_alloc_descs in gpio-omap.c with a follow-up patch. Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | | ARM: omap1: Switch to use MULTI_IRQTony Lindgren2015-05-2019-47/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows us to get a bit further with SPARSE_IRQ and MULTIARCH support. Note that we now also rename omap_irq_flags to omap_l2_irq as that's the omap_irq_flags naming is confusing. It just contains the interrupt number for the l2 irq. Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | | ARM: OMAP1: Switch to use generic irqchip in preparation for sparse IRQTony Lindgren2015-05-201-58/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let's set up things ready for enabling sparse IRQ and remove the omap_read/write usage. Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | | ARM: OMAP1: Move UART defines to prepare for sparse IRQTony Lindgren2015-05-202-5/+3Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These have been indirectly included via asm/irqs.h that has included mach/hardware.h unless SPARSE_IRQ is specified. Let's move them to where the other OMAP serial defines for 8250 are. Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | | | | Merge tag 'arm-soc/for-4.2/soc-take2' of http://github.com/broadcom/stblinux ↵Arnd Bergmann2015-05-229-5/+543
|\ \ \ \ \ | | |_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/soc Merge mach-bcm changes from Florian Fainelli: This pull request contains the following changes: - Rafal adds an additional fault code to be ignored by the kernel on BCM5301X SoC - BCM63138 SMP support which: * common code to control the PMB bus, to be shared with a reset controller driver in drivers/reset * secondary CPU initialization sequence using PMB helpers * small changes suggested by Russell King to allow platforms to disable VFP * tag 'arm-soc/for-4.2/soc-take2' of http://github.com/broadcom/stblinux: ARM: BCM63xx: Add SMP support for BCM63138 ARM: vfp: Add vfp_disable for problematic platforms ARM: vfp: Add include guards ARM: BCM63xx: Add secondary CPU PMB initialization sequence ARM: BCM63xx: Add Broadcom BCM63xx PMB controller helpers ARM: BCM5301X: Ignore another (BCM4709 specific) fault code
| * | | | ARM: BCM63xx: Add SMP support for BCM63138Florian Fainelli2015-05-214-1/+207
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for booting the secondary CPU on BCM63138, this involves: - locating the bootlut to write the reset vector - powering up the second CPU when we need to using the DT-supplied PMB references - disabling VFP when enabled such that we can keep having SMP Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| * | | | ARM: vfp: Add vfp_disable for problematic platformsFlorian Fainelli2015-05-212-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some platforms might not be able to fully utilize VFP when e.g: one CPU out of two in a SMP complex lacks a VFP unit. Adding code to migrate task to the CPU which has a VFP unit would be cumbersome and not performant, instead, just add the ability to disable VFP. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| * | | | ARM: vfp: Add include guardsFlorian Fainelli2015-05-211-0/+5
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| * | | | ARM: BCM63xx: Add secondary CPU PMB initialization sequenceFlorian Fainelli2015-05-211-0/+221
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sequence to initialize a secondary CPU using the BCM63138 PMB is extremely specific and represents much more code than any other on-chip peripheral (AHCI, USB 3.0 or integrated Ethernet switch), as such we keep that code local and utilize Device Tree to lookup all the resources we need from the CPU device tree node. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| * | | | ARM: BCM63xx: Add Broadcom BCM63xx PMB controller helpersFlorian Fainelli2015-05-211-0/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds both common register definitions and helper functions used to issue read/write commands to the Broadcom BCM63xx PMB controller which is used to power on and release from reset internal on-chip peripherals such as the integrated Ethernet switch, AHCI, USB, as well as the secondary CPU core. This is going to be utilized by the BCM63138 SMP code, as well as by the BCM63138 reset controller later. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| * | | | ARM: BCM5301X: Ignore another (BCM4709 specific) fault codeRafał Miłecki2015-05-201-4/+5
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Broadcom ARM devices seem to generate some fault once per boot. We already have an ignoring handler for BCM4707/BCM4708, but BCM4709 generates different code. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* | | | ARM: vf610: enable Cortex-M4 configuration on Vybrid SoCStefan Agner2015-05-204-17/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows to build the Kernel for Vybrid (VF6xx) SoC when ARMv7-M CPU is selected. The resulting image runs on the secondary Cortex-M4 core. This core has equally access to all peripherals as the main Cortex-A5 core. However, there is no resource control mechanism, hence when both cores are used simultaneously, orthogonal device tree's are required. The boot CPU is dependent on the SoC variant. The available boards use mostly variants where the Cortex-A5 is the primary and hence the boot CPU. Booting the secondary Cortex-M4 CPU needs SoC specific registers written. There is no in kernel support for this right now, a external userspace utility called "m4boot" can be used to boot the kernel: m4boot xipImage initramfs.cpio.lzo vf610m4-colibri.dtb Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | | | ARM: introduce ARM_SINGLE_ARMV7M for ARMv7-M platformsStefan Agner2015-05-202-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This introduces a new top level config symbol ARM_SINGLE_ARMV7M for non-MMU, ARMv7-M platforms. It also support multiple ARMv7-M platforms in one kernel image since the cores share the same basic memory layout and interrupt controller. However, this works only if the combined platforms also have a similar (main) memory layout. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | | | ARM: unify MMU/!MMU addruart callsStefan Agner2015-05-202-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the needless differences between MMU/!MMU addruart calls. This allows to use the same addruart macro on SoC level. Useful for SoC consisting of multiple CPUs with and without MMU such as Freescale Vybrid. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | | | Merge branch 'irq/for-arm' of ↵Arnd Bergmann2015-05-208-14/+102
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip into next/soc * 'irq/for-arm' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip: vf610-mscm: Support NVIC parent chip irqchip: nvic: Support hierarchy irq domain genirq: generic chip: Support hierarchy domain genirq: Add irq_chip_(enable/disable)_parent irqdomain: Add non-hierarchy helper irq_domain_set_info
| * | | | irqchip: vf610-mscm: Support NVIC parent chipStefan Agner2015-05-181-6/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support the NVIC interrupt controller as node parent of the MSCM interrupt router. On the dual-core variants of Vybird (VF6xx), the NVIC interrupt controller is used by the Cortex-M4. To support running Linux on this core too, MSCM needs NVIC parent support too. Signed-off-by: Stefan Agner <stefan@agner.ch> Cc: marc.zyngier@arm.com Cc: linux@arm.linux.org.uk Cc: u.kleine-koenig@pengutronix.de Cc: olof@lixom.net Cc: arnd@arndb.de Cc: daniel.lezcano@linaro.org Cc: mark.rutland@arm.com Cc: pawel.moll@arm.com Cc: robh+dt@kernel.org Cc: ijc+devicetree@hellion.org.uk Cc: galak@codeaurora.org Cc: mcoquelin.stm32@gmail.com Cc: linux-arm-kernel@lists.infradead.org Cc: shawn.guo@linaro.org Cc: kernel@pengutronix.de Cc: jason@lakedaemon.net Link: http://lkml.kernel.org/r/1431769465-26867-6-git-send-email-stefan@agner.ch Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * | | | irqchip: nvic: Support hierarchy irq domainStefan Agner2015-05-182-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for hierarchy irq domains. This is required to stack the MSCM interrupt router and the NVIC controller found in Vybrid SoC. Signed-off-by: Stefan Agner <stefan@agner.ch> Cc: marc.zyngier@arm.com Cc: linux@arm.linux.org.uk Cc: u.kleine-koenig@pengutronix.de Cc: olof@lixom.net Cc: arnd@arndb.de Cc: daniel.lezcano@linaro.org Cc: mark.rutland@arm.com Cc: pawel.moll@arm.com Cc: robh+dt@kernel.org Cc: ijc+devicetree@hellion.org.uk Cc: galak@codeaurora.org Cc: mcoquelin.stm32@gmail.com Cc: linux-arm-kernel@lists.infradead.org Cc: shawn.guo@linaro.org Cc: kernel@pengutronix.de Cc: jason@lakedaemon.net Link: http://lkml.kernel.org/r/1431769465-26867-5-git-send-email-stefan@agner.ch Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * | | | genirq: generic chip: Support hierarchy domainStefan Agner2015-05-181-3/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the new helper function irq_domain_set_info to make sure the function irq_domain_set_hwirq_and_chip is being called, which is crucial to save irqdomain specific data to irq_data. Signed-off-by: Stefan Agner <stefan@agner.ch> Cc: marc.zyngier@arm.com Cc: linux@arm.linux.org.uk Cc: u.kleine-koenig@pengutronix.de Cc: olof@lixom.net Cc: arnd@arndb.de Cc: daniel.lezcano@linaro.org Cc: mark.rutland@arm.com Cc: pawel.moll@arm.com Cc: robh+dt@kernel.org Cc: ijc+devicetree@hellion.org.uk Cc: galak@codeaurora.org Cc: mcoquelin.stm32@gmail.com Cc: linux-arm-kernel@lists.infradead.org Cc: shawn.guo@linaro.org Cc: kernel@pengutronix.de Cc: jason@lakedaemon.net Link: http://lkml.kernel.org/r/1431769465-26867-4-git-send-email-stefan@agner.ch Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * | | | genirq: Add irq_chip_(enable/disable)_parentStefan Agner2015-05-182-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add helper irq_chip_enable_parent and irq_chip_disable_parent. The helper implement the default behavior in case irq_enable or irq_disable is not implemented for the parent interrupt chip, which is calling the irq_mask or irq_unmask respectively. Signed-off-by: Stefan Agner <stefan@agner.ch> Cc: marc.zyngier@arm.com Cc: linux@arm.linux.org.uk Cc: u.kleine-koenig@pengutronix.de Cc: olof@lixom.net Cc: arnd@arndb.de Cc: daniel.lezcano@linaro.org Cc: mark.rutland@arm.com Cc: pawel.moll@arm.com Cc: robh+dt@kernel.org Cc: ijc+devicetree@hellion.org.uk Cc: galak@codeaurora.org Cc: mcoquelin.stm32@gmail.com Cc: linux-arm-kernel@lists.infradead.org Cc: shawn.guo@linaro.org Cc: kernel@pengutronix.de Cc: jason@lakedaemon.net Link: http://lkml.kernel.org/r/1431769465-26867-3-git-send-email-stefan@agner.ch Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * | | | irqdomain: Add non-hierarchy helper irq_domain_set_infoStefan Agner2015-05-182-4/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the helper irq_domain_set_info() in a non-domain hierarchy variant. This allows to use the helper for generic chip since not all chips using generic chip support domain hierarchy. Signed-off-by: Stefan Agner <stefan@agner.ch> Cc: marc.zyngier@arm.com Cc: linux@arm.linux.org.uk Cc: u.kleine-koenig@pengutronix.de Cc: olof@lixom.net Cc: arnd@arndb.de Cc: daniel.lezcano@linaro.org Cc: mark.rutland@arm.com Cc: pawel.moll@arm.com Cc: robh+dt@kernel.org Cc: ijc+devicetree@hellion.org.uk Cc: galak@codeaurora.org Cc: mcoquelin.stm32@gmail.com Cc: linux-arm-kernel@lists.infradead.org Cc: shawn.guo@linaro.org Cc: kernel@pengutronix.de Cc: jason@lakedaemon.net Link: http://lkml.kernel.org/r/1431769465-26867-2-git-send-email-stefan@agner.ch Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* | | | | Merge tag 'arm-soc/for-4.2/maintainers' of ↵Arnd Bergmann2015-05-201-0/+1
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | http://github.com/broadcom/stblinux into next/soc This pull request for the MAINTAINERS file contains the following changes: - Brian adds a general "brcmstb" regexp to catch Broadcom Set Top Box related changes throughout the Linux tree * tag 'arm-soc/for-4.2/maintainers' of http://github.com/broadcom/stblinux: MAINTAINERS: add brcmstb regex
| * | | | | MAINTAINERS: add brcmstb regexBrian Norris2015-05-131-0/+1
| | |_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This could probably consolidate a few file listings. And it satisfies the spirit of the highly annoying [1] checkpatch warning for every new file, though it sadly won't quash it. [1] https://lkml.org/lkml/2014/12/17/24 Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* | | | | Merge tag 'zynq-soc-for-4.2' of https://github.com/Xilinx/linux-xlnx into ↵Arnd Bergmann2015-05-203-16/+19
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | next/soc Merge "arm: Xilinx Zynq SoC patches for v4.2" from Michal Simek: - Change SoC reset path - Fix SLCR unlock scheme * tag 'zynq-soc-for-4.2' of https://github.com/Xilinx/linux-xlnx: ARM: zynq: Drop use of slcr_unlock in zynq_slcr_system_restart ARM: zynq: Use restart_handler mechanism for slcr reset
| * | | | | ARM: zynq: Drop use of slcr_unlock in zynq_slcr_system_restartJosh Cartwright2015-05-181-7/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SLCR is unconditionally unlocked early on boot in zynq_slcr_init() and not ever re-locked. As such, it is not necessary to explicitly unlock in the restart codepath. Signed-off-by: Josh Cartwright <joshc@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | | ARM: zynq: Use restart_handler mechanism for slcr resetJosh Cartwright2015-05-183-9/+19
| | |_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By making use of the restart_handler chain mechanism, the SLCR-based reset mechanism can be prioritized amongst other mechanisms available on a particular board. Choose a default high-ish priority of 192 for this restart mechanism. Signed-off-by: Josh Cartwright <joshc@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | | ARM: uniphier: only select TWD for SMPArnd Bergmann2015-05-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes uniphier behave like all the other platforms that support TWD, and only select this driver when SMP is enabled. Without this, we get a compile error on UP builds: arch/arm/kernel/smp_twd.c: In function 'twd_local_timer_of_register': arch/arm/kernel/smp_twd.c:391:20: error: 'setup_max_cpus' undeclared (first use in this function) Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | | | ARM: lpc18xx: define low-level debug symbol for LPC18xx/43xxJoachim Eastwood2015-05-201-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using a dedicated symbol for low-level debugging instead of the arch symbol will make this platform play nice when enabled on a kernel that supports multiple platforms. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | | | | MAINTAINERS: Add entry for NXP LPC18xx/43xx MCUsJoachim Eastwood2015-05-201-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a MAINTAINER entry covering all NXP LPC18xx/43xx machine and drivers files. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | | | | MAINTAINERS: Add entry for STM32 MCUsMaxime Coquelin2015-05-151-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a MAINTAINER entry covering all STM32 machine and drivers files. Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | | | | MAINTAINERS: add entry for ARM ZTE architectureJun Nie2015-05-151-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add entry for ZTE ARM architecture Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | | | | ARM: zx: enable SMP and hotplug for zx296702Jun Nie2015-05-154-0/+241
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bring up the secondary core. Enable hotplug with supporting powering off secondary core. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | | | | ARM: zx: add low level debug support for zx296702Jun Nie2015-05-152-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the UART0 peripheral for low level debug. Only the UART port 0 is currently supported. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | | | | ARM: zx: add basic support for ZTE ZX296702Jun Nie2015-05-155-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add basic code for ZTE ZX296702 platform. [arnd: removed unused zx296702_init_machine function, and changed l2c aux val to default] Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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