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path: root/Documentation/devicetree/bindings/clock/sunxi.txt
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* dt-bindings: Remove leading zeros from bindings notationMarco Franchi2017-11-101-8/+8
* clk: sunxi: Add display and TCON0 clocks driverMaxime Ripard2016-05-121-0/+2
* clk: sunxi: Add TCON channel1 clockMaxime Ripard2016-04-221-0/+1
* clk: sunxi: Add PLL3 clockMaxime Ripard2016-04-221-0/+1
* dt-bindings: clk: sun5i: add DRAM gates compatibleMaxime Ripard2016-04-221-0/+1
* clk: sunxi: Add sun6i/8i display supportJean-Francois Moine2016-04-221-0/+1
* clk: sunxi: Add apb0 gates for H3Krzysztof Adamski2016-02-251-0/+2
* clk: sunxi: add bus gates for A83TVishnu Patekar2016-02-021-0/+1
* clk: sunxi: Add apb0 gates for A83TVishnu Patekar2016-02-021-0/+1
* clk: sunxi: Add VE (Video Engine) module clock driver for sun[457]iChen-Yu Tsai2015-12-081-0/+4
* clk: sunxi: Add H3 clocks supportJens Kuske2015-12-081-0/+2
* clk: sunxi: Add DRAM gates support for sun4i-a10Chen-Yu Tsai2015-12-071-0/+1
* clk: sunxi: Add sun9i A80 cpus (cpu special) clock supportChen-Yu Tsai2015-12-011-0/+1
* clk: sunxi: Add sun9i A80 apbs gates supportChen-Yu Tsai2015-12-011-0/+1
* clk: sunxi: Add support for the H3 usb phy clocksReinder de Haan2015-11-201-0/+1
* clk: sunxi: Add support for the usb-clk on sun8i a23 and a33 SoCsHans de Goede2015-06-021-0/+1
* clk: sunxi: Add muxable ahb factors clock for sun5i and sun7iChen-Yu Tsai2015-03-211-0/+1
* clk: sunxi: Add support for sun9i A80 USB clocks and resetsChen-Yu Tsai2015-02-231-0/+2
* clk: sunxi: Add driver for A80 MMC config clocks/resetsChen-Yu Tsai2015-01-201-1/+24
* clk: sunxi: Add mod0 and mmc module clock support for A80Chen-Yu Tsai2015-01-191-2/+5
* clk: sunxi: Rework MMC phase clocksMaxime Ripard2015-01-141-5/+8
* clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-dividerChen-Yu Tsai2014-12-211-1/+1
* clk: sunxi: Implement A31 PLL6 as a divs clock for 2x outputChen-Yu Tsai2014-11-231-2/+17
* clk: sunxi: Removed unused/incorrect sun6i-a31-apb2-clk driverChen-Yu Tsai2014-11-231-1/+0Star
* clk: sunxi: unify APB1 clockEmilio López2014-11-111-1/+0Star
* clk: sunxi: Add support for bus clock gates on Allwinner A80 SoCChen-Yu Tsai2014-10-211-0/+5
* clk: sunxi: Add support for A80 basic bus clocksChen-Yu Tsai2014-10-211-0/+5
* clk: sunxi: Add sun8i MBUS clock supportChen-Yu Tsai2014-09-271-0/+1
* clk: sunxi: mod0: Introduce MMC proper phase handlingMaxime Ripard2014-09-271-0/+2
* clk: sunxi: Introduce mbus compatibleMaxime Ripard2014-09-271-0/+1
* clk: sunxi: sun6i-a31-apb0-gates: Add A23 APB0 supportChen-Yu Tsai2014-07-151-0/+1
* clk: sunxi: Add A23 APB0 divider clock supportChen-Yu Tsai2014-07-071-0/+1
* clk: sunxi: Add A23 clocks supportChen-Yu Tsai2014-07-041-0/+5
* clk: sunxi: document PRCM clock compatible stringsBoris BREZILLON2014-06-111-0/+3
* clk: sunxi: document new A31 USB clock compatibleEmilio López2014-06-111-0/+1
* clk: sunxi: Add new clock compatiblesMaxime Ripard2014-02-181-18/+18
* clk: sunxi: Add Allwinner A20/A31 GMAC clock unitChen-Yu Tsai2014-02-181-0/+30
* clk: sunxi: Add support for PLL6 on the A31Maxime Ripard2014-02-181-0/+1
* clk: sunxi: Add USB clock register defintionsRoman Byshko2014-02-181-0/+5
* clk: sunxi: update clock-output-names dt binding documentationChen-Yu Tsai2014-02-031-6/+26
* clk: sunxi: Allwinner A20 output clock supportChen-Yu Tsai2013-12-281-0/+1
* clk: sunxi: mod0 supportEmilio López2013-12-281-1/+4
* clk: sunxi: add PLL5 and PLL6 supportEmilio López2013-12-281-0/+2
* clk: sunxi: add gating support to PLL1Emilio López2013-12-281-1/+1
* Documentation: dt: Remove clock gates IDs list for Allwinner SoCsMaxime Ripard2013-10-111-2/+2
* clk: sunxi: Add Allwinner A20 gatesMaxime Ripard2013-08-261-0/+3
* clk: sunxi: Add A31 clocks supportMaxime Ripard2013-08-261-0/+6
* clk: sunxi: Add A10s gatesMaxime Ripard2013-08-261-0/+3
* clk: sun5i: Add compatibles for Allwinner A13Maxime Ripard2013-05-291-104/+13Star
* clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gatesEmilio López2013-04-041-1/+108
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-01 07:43:33 +0200