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path: root/Documentation/devicetree/bindings/clock/sunxi.txt
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* clk: sunxi: Add sun8i MBUS clock supportChen-Yu Tsai2014-09-271-0/+1
* clk: sunxi: mod0: Introduce MMC proper phase handlingMaxime Ripard2014-09-271-0/+2
* clk: sunxi: Introduce mbus compatibleMaxime Ripard2014-09-271-0/+1
* clk: sunxi: sun6i-a31-apb0-gates: Add A23 APB0 supportChen-Yu Tsai2014-07-151-0/+1
* clk: sunxi: Add A23 APB0 divider clock supportChen-Yu Tsai2014-07-071-0/+1
* clk: sunxi: Add A23 clocks supportChen-Yu Tsai2014-07-041-0/+5
* clk: sunxi: document PRCM clock compatible stringsBoris BREZILLON2014-06-111-0/+3
* clk: sunxi: document new A31 USB clock compatibleEmilio López2014-06-111-0/+1
* clk: sunxi: Add new clock compatiblesMaxime Ripard2014-02-181-18/+18
* clk: sunxi: Add Allwinner A20/A31 GMAC clock unitChen-Yu Tsai2014-02-181-0/+30
* clk: sunxi: Add support for PLL6 on the A31Maxime Ripard2014-02-181-0/+1
* clk: sunxi: Add USB clock register defintionsRoman Byshko2014-02-181-0/+5
* clk: sunxi: update clock-output-names dt binding documentationChen-Yu Tsai2014-02-031-6/+26
* clk: sunxi: Allwinner A20 output clock supportChen-Yu Tsai2013-12-281-0/+1
* clk: sunxi: mod0 supportEmilio López2013-12-281-1/+4
* clk: sunxi: add PLL5 and PLL6 supportEmilio López2013-12-281-0/+2
* clk: sunxi: add gating support to PLL1Emilio López2013-12-281-1/+1
* Documentation: dt: Remove clock gates IDs list for Allwinner SoCsMaxime Ripard2013-10-111-2/+2
* clk: sunxi: Add Allwinner A20 gatesMaxime Ripard2013-08-261-0/+3
* clk: sunxi: Add A31 clocks supportMaxime Ripard2013-08-261-0/+6
* clk: sunxi: Add A10s gatesMaxime Ripard2013-08-261-0/+3
* clk: sun5i: Add compatibles for Allwinner A13Maxime Ripard2013-05-291-104/+13Star
* clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gatesEmilio López2013-04-041-1/+108
* clk: sunxi: rename compatible stringsEmilio López2013-03-271-11/+11
* clk: arm: sunxi: Add a new clock driver for sunxi SOCsEmilio López2013-03-271-0/+44
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