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* Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds2019-07-2015-142/+3644
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM Devicetree updates from Olof Johansson: "We continue to see a lot of new material. I've highlighted some of it below, but there's been more beyond that as well. One of the sweeping changes is that many boards have seen their ARM Mali GPU devices added to device trees, since the DRM drivers have now been merged. So, with the caveat that I have surely missed several great contributions, here's a collection of the material this time around: New SoCs: - Mediatek mt8183 (4x Cortex-A73 + 4x Cortex-A53) - TI J721E (2x Cortex-A72 + 3x Cortex-R5F + 3 DSPs + MMA) - Amlogic G12B (4x Cortex-A73 + 2x Cortex-A53) New Boards / platforms: - Aspeed BMC support for a number of new server platforms - Kontron SMARC SoM (several i.MX6 versions) - Novtech's Meerkat96 (i.MX7) - ST Micro Avenger96 board - Hardkernel ODROID-N2 (Amlogic G12B) - Purism Librem5 devkit (i.MX8MQ) - Google Cheza (Qualcomm SDM845) - Qualcomm Dragonboard 845c (Qualcomm SDM845) - Hugsun X99 TV Box (Rockchip RK3399) - Khadas Edge/Edge-V/Captain (Rockchip RK3399) Updated / expanded boards and platforms: - Renesas r7s9210 has a lot of new peripherals added - Fixes and polish for Rockchip-based Chromebooks - Amlogic G12A has a lot of peripherals added - Nvidia Jetson Nano sees various fixes and improvements, and is now at feature parity with TX1" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (586 commits) ARM: dts: gemini: Set DIR-685 SPI CS as active low ARM: dts: exynos: Adjust buck[78] regulators to supported values on Arndale Octa ARM: dts: exynos: Adjust buck[78] regulators to supported values on Odroid XU3 family ARM: dts: exynos: Move Mali400 GPU node to "/soc" ARM: dts: exynos: Fix imprecise abort on Mali GPU probe on Exynos4210 arm64: dts: qcom: qcs404: Add missing space for cooling-cells property arm64: dts: rockchip: Fix USB3 Type-C on rk3399-sapphire arm64: dts: rockchip: Update DWC3 modules on RK3399 SoCs arm64: dts: rockchip: enable rk3328 watchdog clock ARM: dts: rockchip: add display nodes for rk322x ARM: dts: rockchip: fix vop iommu-cells on rk322x arm64: dts: rockchip: Add support for Hugsun X99 TV Box arm64: dts: rockchip: Define values for the IPA governor for rock960 arm64: dts: rockchip: Fix multiple thermal zones conflict in rk3399.dtsi arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs arm64: dts: rockchip: improve rk3328-roc-cc rgmii performance. Revert "ARM: dts: rockchip: set PWM delay backlight settings for Minnie" ARM: dts: rockchip: Configure BT_DEV_WAKE in on rk3288-veyron arm64: dts: qcom: sdm845-cheza: add initial cheza dt ARM: dts: msm8974-FP2: Add vibration motor ...
| * Merge tag 'qcom-arm64-for-5.3-2' of ↵Olof Johansson2019-06-286-0/+2251
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt Qualcomm ARM64 Updates for v5.3 Part 2 * Add SDM845 Cheza support * Add TSENS controller and thermal zones for QCS404 * tag 'qcom-arm64-for-5.3-2' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: arm64: dts: qcom: qcs404: Add missing space for cooling-cells property arm64: dts: qcom: sdm845-cheza: add initial cheza dt arm64: dts: qcom: qcs404: Add thermal zones for each sensor arm64: dts: qcom: qcs404: Add tsens controller Signed-off-by: Olof Johansson <olof@lixom.net>
| | * arm64: dts: qcom: qcs404: Add missing space for cooling-cells propertyNiklas Cassel2019-06-281-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There should be a space both before and after the equal sign. Add a missing space for the cooling cells property. Fixes: f48cee3239a1 ("arm64: dts: qcom: qcs404: Add thermal zones for each sensor") Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Acked-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: sdm845-cheza: add initial cheza dtRob Clark2019-06-255-0/+1979
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is essentialy a squash of a bunch of history of cheza dt updates from chromium kernel, some of which were themselves squashes of history from older chromium kernels. I don't claim any credit other than wanting to more easily boot upstream kernel on cheza to have an easier way to test upstream driver work ;-) I've added below in Cc tags all the original actual authors (apologies if I missed any). Cc: Douglas Anderson <dianders@chromium.org> Cc: Sibi Sankar <sibis@codeaurora.org> Cc: Evan Green <evgreen@chromium.org> Cc: Matthias Kaehlcke <mka@chromium.org> Cc: Abhinav Kumar <abhinavk@codeaurora.org> Cc: Brian Norris <briannorris@chromium.org> Cc: Venkat Gopalakrishnan <venkatg@codeaurora.org> Cc: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: qcs404: Add thermal zones for each sensorAmit Kucheria2019-06-251-0/+252
| | | | | | | | | | | | | | | | | | | | | | | | qcs404 has 10 sensors connected to the single TSENS IP. Define a thermal zone for each of those sensors to expose the temperature of each zone. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: qcs404: Add tsens controllerAmit Kucheria2019-06-251-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | qcs404 has a single TSENS IP block with 10 sensors. The calibration data is stored in an eeprom (qfprom) that is accessed through the nvmem framework. We add the qfprom node to allow the tsens sensors to be calibrated correctly. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| * | Merge tag 'qcom-arm64-for-5.3' of ↵Olof Johansson2019-06-2511-142/+1392
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt Qualcomm ARM64 Updates for v5.3 * Switch to use second gen PON on PM8998 * Add PSCI cupidle states for MSM8996, MSM8998,and SDM845 * Add MSM8996 UFS phy reset controller * Add propre cpu capacity scaling on MSM8996 * Fixups for APR domain, legacy clocks, and PSCI entry latency on MSM8996 * Enable SMMUs on MSM8996 * Add Dragonboard 845C * Add Q6V5, GPU, GMU, and AOSS QMP node on SDM845 * Fixup CPU topology on SDM845 * Change USB1 to be peripheral on SDM845 MTP * Add PCIe Phy, RC nodes, ANOC1 SMMU, and RPMPD node on MSM8998 * Update coresight bindings for MSM8916 * Update idle state names and entry-method on MSM8916 * Add PCIe, RPMPD, LPASS, Q6, TCSR, TuringCC, PSCI cpuidle states, and CDSP on QCS404 * Add reset-cells property to QCS404 GCC node * Fixup s3 max voltage, l3 min voltage, drive strength typo, and s3 supply definition on QCS404-evb * Fixup ADC outputs and VADC calibration on PMS405 * tag 'qcom-arm64-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (39 commits) arm64: dts: qcom: qcs404-evb: fix vdd_apc supply arm64: dts: qcom: pm8998: Use qcom,pm8998-pon binding for second gen pon arm64: dts: qcom: msm8996: Enable SMMUs arm64: dts: qcom: msm8996: Correct apr-domain property arm64: dts: qcom: Add Dragonboard 845c arm64: dts: qcom: qcs404-evb: Enable PCIe arm64: dts: qcom: qcs404: Add PCIe related nodes arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes arm64: dts: qcom: msm8998: Add ANOC1 SMMU node arm64: dts: qcom: msm8996: Stop using legacy clock names arm64: dts: msm8996: fix PSCI entry-latency-us arm64: dts: qcom: msm8998: Add PSCI cpuidle low power states arm64: dts: qcom: sdm845: Add Q6V5 MSS node arm64: dts: qcom: Add AOSS QMP node arm64: dts: qcom-qcs404: Add reset-cells to GCC node arm64: dts: qcom-msm8916: Update coresight DT bindings arm64: dts: qcom: msm8998: Add rpmpd node arm64: dts: qcom: qcs404: Add rpmpd node arm64: dts: qcom: qcs404: Move lpass and q6 into soc arm64: dts: qcom: qcs404: Fully describe the CDSP ... Signed-off-by: Olof Johansson <olof@lixom.net>
| | * arm64: dts: qcom: qcs404-evb: fix vdd_apc supplyJorge Ramirez-Ortiz2019-06-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The invalid definition in the supply causes the Qualcomm's EVB-1000 and EVB-4000 not to boot. Fix the boot issue by correctly defining the supply: vdd_s3 (namely "vdd_apc") is actually connected to vph_pwr. Reported-by: Niklas Cassel <niklas.cassel@linaro.org> Tested-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: pm8998: Use qcom,pm8998-pon binding for second gen ponJohn Stultz2019-06-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This changes pm8998 to use the new qcom,pm8998-pon compatible string for the pon in order to support the gen2 pon functionality properly. Cc: Andy Gross <agross@kernel.org> Cc: David Brown <david.brown@linaro.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Amit Pundir <amit.pundir@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Sebastian Reichel <sre@kernel.org> Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: msm8996: Enable SMMUsBjorn Andersson2019-06-191-6/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | Enable SMMUs on 8996 now that the WRZ workaround in the arm-smmu driver has landed. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: msm8996: Correct apr-domain propertyBjorn Andersson2019-06-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The domain specifier was changed from using "reg" to "qcom,apr-domain", update the dts accordingly. Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
| | * arm64: dts: qcom: Add Dragonboard 845cBjorn Andersson2019-06-182-0/+558
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds an initial dts for the Dragonboard 845. Supported functionality includes Debug UART, UFS, USB-C (peripheral), USB-A (host), microSD-card and Bluetooth. Initializing the SMMU is clearing the mapping used for the splash screen framebuffer, which causes the board to reboot. This can be worked around using: fastboot oem select-display-panel none Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Tested-by: Vinod Koul <vkoul@kernel.org> Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
| | * arm64: dts: qcom: qcs404-evb: Enable PCIeBjorn Andersson2019-06-181-0/+26
| | | | | | | | | | | | | | | | | | Enable the PCIe PHY and controller found on the QCS404 EVB. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
| | * arm64: dts: qcom: qcs404: Add PCIe related nodesBjorn Andersson2019-06-181-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | The QCS404 has a PCIe2 PHY and a Qualcomm PCIe controller, define these to for the platform. Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
| | * arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodesMarc Gonzalez2019-06-171-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add MSM8998 PCIe QMP PHY and PCIe root complex DT nodes. Based on the following DTS downstream: https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm8998.dtsi?h=LE.UM.1.3.r3.25#n2537 Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
| | * arm64: dts: qcom: msm8998: Add ANOC1 SMMU nodeMarc Gonzalez2019-06-171-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MSM8998 ANOC1(*) SMMU services BLSP2, PCIe, UFS, and USB. (*) Aggregate Network-on-Chip #1 Based on the following DTS downstream: https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm-arm-smmu-8998.dtsi?h=LE.UM.1.3.r3.25#n18 Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
| | * arm64: dts: qcom: msm8996: Stop using legacy clock namesBjorn Andersson2019-06-121-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | MDSS and its friends complain about the DTS is using legacy clock names, update these to silence the warnings. Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
| | * arm64: dts: msm8996: fix PSCI entry-latency-usNiklas Cassel2019-06-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current entry-latency-us is too short. The proper way to convert between the device tree properties from the vendor tree to the upstream PSCI device tree properties is: entry-latency-us = qcom,time-overhead - qcom,latency-us which gives entry-latency-us = 210 - 80 = 130 Fixes: f6aee7af59b6 ("arm64: dts: qcom: msm8996: Add PSCI cpuidle low power states") Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
| | * arm64: dts: qcom: msm8998: Add PSCI cpuidle low power statesAmit Kucheria2019-06-121-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device bindings for cpuidle states for cpu devices. [marc: rebase, fix arm,psci-suspend-param, fix entry-latency-us] Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
| | * arm64: dts: qcom: sdm845: Add Q6V5 MSS nodeSibi Sankar2019-06-121-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds Q6V5 MSS remoteproc node for SDM845 SoCs. Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
| | * arm64: dts: qcom: Add AOSS QMP nodeBjorn Andersson2019-06-121-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AOSS QMP provides a number of power domains, used for QDSS and PIL, add the node for this. Tested-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
| | * arm64: dts: qcom-qcs404: Add reset-cells to GCC nodeAndy Gross2019-06-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a reset-cells property to the gcc controller on the QCS404. Without this in place, we get warnings like the following if nodes reference a gcc reset: arch/arm64/boot/dts/qcom/qcs404.dtsi:261.38-310.5: Warning (resets_property): /soc@0/remoteproc@b00000: Missing property '#reset-cells' in node /soc@0/clock-controller@1800000 or bad phandle (referred from resets[0]) also defined at arch/arm64/boot/dts/qcom/qcs404-evb.dtsi:82.18-84.3 DTC arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb arch/arm64/boot/dts/qcom/qcs404.dtsi:261.38-310.5: Warning (resets_property): /soc@0/remoteproc@b00000: Missing property '#reset-cells' in node /soc@0/clock-controller@1800000 or bad phandle (referred from resets[0]) also defined at arch/arm64/boot/dts/qcom/qcs404-evb.dtsi:82.18-84.3 Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom-msm8916: Update coresight DT bindingsLeo Yan2019-06-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CoreSight DT bindings have been updated, thus the old compatible strings are obsolete and the drivers will report warning if DTS uses these obsolete strings. This patch switches to the new bindings for CoreSight dynamic funnel, so can dismiss warning during initialisation. Cc: Andy Gross <agross@kernel.org> Cc: David Brown <david.brown@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: msm8998: Add rpmpd nodeSibi Sankar2019-05-301-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the rpmpd node on the msm8998 and define the available levels. Reviewed-by: Jeffrey Hugo <jhugo@codeaurora.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> [bjorn: dropped use of level defines, to allow merging in parallel] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: qcs404: Add rpmpd nodeBjorn Andersson2019-05-301-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the rpmpd node on the qcs404 and define the available levels. Reviewed-by: Jeffrey Hugo <jhugo@codeaurora.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> [sibis: fixup available levels] Signed-off-by: Sibi Sankar <sibis@codeaurora.org> [bjorn: dropped use of level defines, to allow merging in parallel] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: qcs404: Move lpass and q6 into socBjorn Andersson2019-05-301-62/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although we don't describe lpass and wcss with all the details needed to control them in a Trustzone-less environment, move them under soc in order to tidy up the structure and prepare for describing them fully. Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: qcs404: Fully describe the CDSPBjorn Andersson2019-05-301-31/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add all the properties needed to describe the CDSP for both the Trustzone and non-Trustzone based remoteproc case, allowing any child devices to be described once by just overriding the compatible to match the firmware available on the board. Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: qcs404: Add TCSR nodeBjorn Andersson2019-05-301-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | The bus halt registers in TCSR are referenced as a syscon device, add these so that we can reference them from the remoteproc nodes. Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: qcs404-evb: Mark CDSP clocks protectedBjorn Andersson2019-05-301-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the Trustzone based CDSP remoteproc driver these clocks are controlled elsewhere and as they are not enabled by anything in Linux the clock framework will turn them off during lateinit. This results in issues either to later start the CDSP, using the Trustzone interface, or if the CDSP is already running it will crash. Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: sdm845: Add PSCI cpuidle low power statesRaju P.L.S.S.S.N2019-05-301-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device bindings for cpuidle states for cpu devices. Cc: <mkshah@codeaurora.org> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Evan Green <evgreen@chromium.org> Signed-off-by: Raju P.L.S.S.S.N <rplsssn@codeaurora.org> [amit: rename the idle-states to more generic names and fixups] Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: msm8996: Add proper capacity scaling for the cpusAmit Kucheria2019-05-301-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | msm8996 features 4 cpus - 2 in each cluster. However, all cpus implement the same microarchitecture and the two clusters only differ in the maximum frequency attainable by the CPUs. Add capacity-dmips-mhz property to allow the topology code to determine the actual capacity by taking into account the highest frequency for each CPU. Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Suggested-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: msm8996: Add PSCI cpuidle low power statesAmit Kucheria2019-05-301-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device bindings for cpuidle states for cpu devices. msm8996 features 4 cpus - 2 in each cluster. However, all cpus implement the same microarchitecture and the two clusters only differ in the maximum frequency attainable by the CPUs. Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: msm8916: Use more generic idle state namesAmit Kucheria2019-05-301-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of using Qualcomm-specific terminology, use generic node names for the idle states that are easier to understand. Move the description into the "idle-state-name" property. Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: msm8916: Add entry-method property for the idle-states nodeAmit Kucheria2019-05-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The idle-states binding documentation[1] mentions that the 'entry-method' property is required on 64-bit platforms and must be set to "psci". [1] Documentation/devicetree/bindings/arm/idle-states.txt (see idle-states node) Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: qcs404: Add turingcc nodeBjorn Andersson2019-05-301-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a node describing the Turing Clock Controller of the QCS404. Given the default access restriction the node is left disabled. Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: qcs404: Add PSCI cpuidle low power statesNiklas Cassel2019-05-301-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device bindings for cpuidle states for cpu devices. Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> [amit: rename the idle-states to more generic names and fixups] Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: sdm845: Add zap shader region for GPUJordan Crouse2019-05-301-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some Adreno GPU targets require a special zap shader to bring the GPU out of secure mode. Define a region to allocate and store the zap shader. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> [bjorn: Rebase ontop of recent reserved-memory patch] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: sdm845: Add gpu and gmu device nodesJordan Crouse2019-05-301-0/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the nodes to describe the Adreno GPU and GMU devices for sdm845. Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> [bjorn: Added required gx power-domain] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: sdm845-mtp: Make USB1 peripheralBjorn Andersson2019-05-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MTP is a "mobile reference device", as such the default operation is to use fastboot to boot/flash software onto it and the common case is thereby that we boot with a USB cable connected downstream from a PC or a hub. And without support for the PMI8998 charger block VBUS will not be driven by the device. Switch to peripheral until we can enable OTG. Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: qcs404-evb: increase s3 max voltageNiklas Cassel2019-05-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Increase s3 max voltage in accordance to QCS404 CPR Fusing Guide Rev 6.0 Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: qcs404-evb: fix l3 min voltageNiklas Cassel2019-05-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current l3 min voltage level is not supported by the regulator (the voltage is not a multiple of the regulator step size), so a driver requesting this exact voltage would fail, see discussion in: https://patchwork.kernel.org/comment/22461199/ It was agreed upon to set a min voltage level that is a multiple of the regulator step size. There was actually a patch sent that did this: https://patchwork.kernel.org/patch/10819313/ However, the commit 331ab98f8c4a ("arm64: dts: qcom: qcs404: Fix voltages l3") that was applied is not identical to that patch. Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: pms405: Rename adc outputs as per schematicsAmit Kucheria2019-05-301-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The adc outputs shouldn't contain information about their configuration e.g. 100K pull-up, but just reflect the name of the signal in the schematics. Making them labels also allows us to overwrite their configuration in board-specific DTs. Sort them by order as used in adc5_chans_rev2, while we're at it. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: pms405: calibrate the VADC correctlyAmit Kucheria2019-05-301-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set the qcom,ratiometric property to make the VADC use the VDD reference (1.875V) and GND for channel calibration of the temperature channels instead of 1.25V. Allow a 200us delay between the AMUX configuration and ADC starting conversion using qcom,hw-settle-time as described in documentation. Fixes: 041b9a7b9fdb ("arm64: dts: pms405: Export PMIC temperature to thermal framework") Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: sdm845: Fix up CPU topologyAmit Kucheria2019-05-301-6/+4Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SDM845 implements ARM's Dynamiq architecture that allows the big and LITTLE cores to exist in a single cluster sharing the L3 cache. Fix the cpu-map to put all cpus into a single cluster. Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: qcom: qcs404-evb: Fix typoVinod Koul2019-05-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the typo "dreive-strength" and use correct property drive-strength Fixes: 7241ab944da3 ("arm64: dts: qcom: qcs404: Add sdcc1 node") Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| | * arm64: dts: msm8996: Add UFS PHY reset controllerEvan Green2019-05-301-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the reset controller for the UFS controller, and wire it up so that the UFS PHY can initialize itself without relying on implicit sequencing between the two drivers. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Evan Green <evgreen@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
| * | arm64: qcom: qcs404: Add reset-cells to GCC nodeAndy Gross2019-06-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a reset-cells property to the gcc controller on the QCS404. Without this in place, we get warnings like the following if nodes reference a gcc reset: arch/arm64/boot/dts/qcom/qcs404.dtsi:261.38-310.5: Warning (resets_property): /soc@0/remoteproc@b00000: Missing property '#reset-cells' in node /soc@0/clock-controller@1800000 or bad phandle (referred from resets[0]) also defined at arch/arm64/boot/dts/qcom/qcs404-evb.dtsi:82.18-84.3 DTC arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb arch/arm64/boot/dts/qcom/qcs404.dtsi:261.38-310.5: Warning (resets_property): /soc@0/remoteproc@b00000: Missing property '#reset-cells' in node /soc@0/clock-controller@1800000 or bad phandle (referred from resets[0]) also defined at arch/arm64/boot/dts/qcom/qcs404-evb.dtsi:82.18-84.3 Signed-off-by: Andy Gross <agross@kernel.org> Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
* | | arm64: dts: msm8998-mtp: Add pm8005_s1 regulatorJeffrey Hugo2019-06-181-0/+17
|/ / | | | | | | | | | | | | | | | | | | | | The pm8005_s1 is VDD_GFX, and needs to be on to enable the GPU. This should be hooked up to the GPU CPR, but we don't have support for that yet, so until then, just turn on the regulator and keep it on so that we can focus on basic GPU bringup. Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* / treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 284Thomas Gleixner2019-06-0522-198/+22Star
|/ | | | | | | | | | | | | | | | | | | | | | | | | Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 and only version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 294 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.825281744@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* arm64: dts: msm8998: thermal: Restrict thermal zone name length to under 20Amit Kucheria2019-04-261-2/+2
| | | | | | | | | The thermal core restricts names of thermal zones to under 20 characters. Fix the names for a couple of msm8998 thermal zones. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Tested-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Andy Gross <agross@kernel.org>
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