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* arm64: dts: rockchip: enable hdmi on rk3399-puma-haikouJakob Unterwurzacher2018-05-031-0/+21
| | | | | | | | | | | The Puma-haikou combo supports hdmi output, so enable the hdmi controller and vop controllers on it. Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> Cc: linux-rockchip@lists.infradead.org Cc: Heiko Stuebner <heiko@sntech.de> Cc: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* arm64: dts: rockchip: use canonical compatible for touchpad/touchscreen on ↵Dmitry Torokhov2018-05-031-2/+2
| | | | | | | | | | | gru-kevin "atmel,atmel_mxt_tp" and "atmel,atmel_mxt_ts" are ChromeOS inventions, let's replace them with canonical compatible string "atmel,maxtouch". Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* arm64: dts: rockchip: add clocks in iommu nodesJeffy Chen2018-04-163-2/+32
| | | | | | | | Add clocks in iommu nodes, since we are going to control clocks in rockchip iommu driver. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* arm64: dts: rockchip: add usb3-phy otg-port support for rk3399Enric Balletbo i Serra2018-04-161-4/+4
| | | | | | | Add the usb3 phyter for the USB3.0 OTG controller. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* arm64: dts: rockchip: remove PCIe assigned-clocks in excavator baseboardVicente Bergas2018-04-161-3/+0Star
| | | | | | | | | | | Reference clock is needed for pcie_phy, not pcie controller. Actually pcie_phy doesn't need this since rk3399 clock driver already take care of this. Suggested-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Vicente Bergas <vicencb@gmail.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* arm64: dts: rockchip: move rk3399-sapphire PCIe to excavator baseboardVicente Bergas2018-04-162-15/+15
| | | | | | | | The PCIe signals are routed through the connector to the baseboard. Signed-off-by: Vicente Bergas <vicencb@gmail.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* arm64: dts: rockchip: assign clock rate for cpll child clocks on rk3399Lin Huang2018-04-162-6/+16
| | | | | | | | | | | | | | | | | | | These clocks do not assign default clock frequency, and use the default cru register value to get frequency, so if cpll increase frequency, these clocks also increase their frequency, that may exceed their signed off frequency. So assign default clock for them to avoid it. NOTE: on none of the boards currently in mainline do we expect CPLL to be anything other than 800 MHz, but some future boards might have it. It's still good to be explicit about the clock rates to make diffing against future boards easier and also to rely less on BIOS muxing. Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* arm64: dts: rockchip: enable typec-phy0 for rk3399-puma-haikouEnric Balletbo i Serra2018-04-161-0/+4
| | | | | | | | | | | | | | | | | | Commit c301b327aea898af ("arm64: dts: rockchip: add usb3-phy otg-port support for rk3399") caused a regression regarding the USB3. During boot, the following message appears a few times: dwc3: failed to initialize core The driver is deferred waiting for the typec-phy, but this never happens beause is disabled. So, enable it. The offending commit was reverted in 4.16-rc but can be re-applied after enabling the typec phys. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* arm64: dts: rockchip: enable typec-phy1 for rk3399-pumaEnric Balletbo i Serra2018-04-161-0/+4
| | | | | | | | | | | | | | | | | | Commit c301b327aea898af ("arm64: dts: rockchip: add usb3-phy otg-port support for rk3399") caused a regression regarding the USB3. During boot, the following message appears a few times: dwc3: failed to initialize core The driver is deferred waiting for the typec-phy, but this never happens beause is disabled. So, enable it. The offending commit was reverted in 4.16-rc but can be re-applied after enabling the typec phys. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* arm64: dts: rockchip: enable typec-phy for rk3399-fireflyEnric Balletbo i Serra2018-04-161-0/+8
| | | | | | | | | | | | | | | | | Commit c301b327aea898af ("arm64: dts: rockchip: add usb3-phy otg-port support for rk3399") caused a regression regarding the USB3. During boot, the following message appears a few times: dwc3: failed to initialize core The driver is deferred waiting for the typec-phy, but this never happens beause is disabled. So, enable it. The offending commit was reverted in 4.16-rc but can be re-applied after enabling the typec phys. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* arm64: dts: rockchip: enable typec-phy for rk3399-sapphireEnric Balletbo i Serra2018-04-161-0/+8
| | | | | | | | | | | | | | | | | | | Commit c301b327aea898af ("arm64: dts: rockchip: add usb3-phy otg-port support for rk3399") caused a regression regarding the USB3 type-A port. During boot, the following message appears a few times: dwc3: failed to initialize core The driver is deferred waiting for the typec-phy, but this never happens bceause is disabled. So, enable it. The offending commit was reverted in 4.16-rc but can be re-applied after enabling the typec phys. Reported-by: Vicente Bergas <vicencb@gmail.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Tested-by: Vicente Bergas <vicencb@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* Merge tag 'armsoc-dt' of ↵Linus Torvalds2018-04-0612-72/+981
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC device tree updates from Arnd Bergmann: "This is the usual set of changes for device trees, with over 700 non-merged changesets. There is an ongoing set of dtc warning fixes and the usual bugfixes, cleanups and added device support. The most interesting bit as usual is support for new machines listed below: - The Allwinner H6 makes its debut with the Pine-H64 board, and we get two new machines based on its older siblings: the H5 based OrangePi Zero+ and the A64 based Teres-I Laptop from Olimex. On the 32-bit side, we add The Olimex som204 based on Allwinner A20, and the Banana Pi M2 Zero development board (based on H2). - NVIDIA adds support for Tegra194 aka "Xavier", plus their p2972 development board and p2888 CPU module. - The Nuvoton npcm750 is a BMC that was newly added, for now we only support running on the evaluation board. - STmicroelectronics stm32 gains support for the stm32mp157c and two evaluation boards. - The Toradex Colibri board family grows a few members based on the i.MX6ULL variant. - The Advantec DMS-BA16 is a Qseven module using the NXP i.MX6 family of chips. - The Phytec phyBOARD Mira is a family of industrial boards based on i.MX6. For now, four models get added. - TI am335x based PDU-001 is an industrial embedded machine used for traffic monitoring - The Aspeed platform now supports running on the BMC on the Qualcomm Centriq 2400 server - Samsung Exynos4 based Galaxy S3 is a family of mobile phones Qualcomm msm8974 based Galaxy S5 is a rather different phone made by the same company. - The Xilinx Zynq and ZynqMP platforms now gained a lot of dts file for the various boards made by Xilinx themselves, as well as the Digilent Zybo Z7. - The ARM Versatile family now supports the "IB2" interface board. - The Renesas H2 based "Stout" and the H3 based Salvator-X are more evaluation boards named after a kind of beer, as most of them are. The r8a77980 (V3H) based "Condor" apparently doesn't follow that tradition. ;-) - ROC-RK3328-CC is a simple developement board from the Libre Computer Project, based on the Rockchips RK3328 SoC - Haiku is another development board plus Qseven module based on Rockchips RK3368 and made by Theobroma Systems" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (701 commits) arm: dts: modify Nuvoton NPCM7xx device tree structure arm: dts: modify Makefile NPCM750 configuration name arm: dts: modify clock binding in NPCM750 device tree arm: dts: modify timer register size in NPCM750 device tree arm: dts: modify UART compatible name in NPCM750 device tree arm: dts: add watchdog device to NPCM750 device tree arm64: dts: uniphier: add ethernet node for PXs3 ARM: dts: uniphier: add pinctrl groups of ethernet for second instance arm: dts: kirkwood*.dts: use SPDX-License-Identifier for board using GPL-2.0+ arm: dts: kirkwood*.dts: use SPDX-License-Identifier for boards using GPL-2.0+/MIT arm: dts: kirkwood*.dts: use SPDX-License-Identifier for boards using GPL-2.0 arm: dts: armada-385-turris-omnia: use SPDX-License-Identifier arm: dts: armada-385-db-ap: use SPDX-License-Identifier arm: dts: armada-388-rd: use SPDX-License-Identifier arm: dts: armada-xp-db-xc3-24g4xg: use SPDX-License-Identifier arm: dts: armada-xp-db-dxbc2: use SPDX-License-Identifier arm: dts: armada-370-db: use SPDX-License-Identifier arm: dts: armada-*.dts: use SPDX-License-Identifier for most of the Armada based board arm: dts: armada-xp-98dx: use SPDX-License-Identifier for prestara 98d SoCs arm: dts: armada-*.dtsi: use SPDX-License-Identifier for most of the Armada SoCs ...
| * Merge tag 'v4.17-rockchip-dts64-1' of ↵Arnd Bergmann2018-03-2812-72/+981
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt Pull "Rockchip dts64 changes for 4.17" from Heiko Stübner: The rk3399 gained support its Cadence displayport controller and some minor additions like pins for 2ch i2s0 and the cif test clocks as well as a default rate for ACLK_VIO that should be 400MHz according to the TRM. The rk3328 got uart dmas fixed - a non-critical fix, as nobody was using that so far. New boards are the rk3328-based roc-rk3328-cc, the rk3368-based Lion-SOM + baseborad from Theobroma Systems and a standalone variant of the Sapphire board, as a lot of people where using that without the Exkavator baseboard. Sapphire also saw a lot of small cleanups of things that are not part of the actual Sapphire board, but the baseboard instead. The rk3399-puma board got i2s and tsadc support and Gru got its DP node enabled. * tag 'v4.17-rockchip-dts64-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: remove keep-power-in-suspend from sdhci of rk3399-sapphire arm64: dts: rockchip: assign clock rate for ACLK_VIO on rk3399 arm64: dts: rockchip: add a standalone version of the rk3399 sapphire arm64: dts: rockchip: move rk3399-sapphire pwr_btn to daughterboard arm64: dts: rockchip: move rk3399-sapphire i2s2 to daughterboard arm64: dts: rockchip: move rk3399-sapphire sdio to excavator baseboard arm64: dts: rockchip: enable I2S codec on rk3399-puma-haikou arm64: dts: rockchip: move i2s0 node from baseboard to SoM on rk3399-puma arm64: dts: rockchip: vdd_log on rk3399-sapphire is not an i2c slave arm64: dts: rockchip: add Haikou baseboard with RK3368-uQ7 SoM arm64: dts: rockchip: add RK3368-uQ7 (Lion) SoM dt-bindings: add RK3368-uQ7 SoM and EVK base board arm64: dts: rockchip: Fix RK3328 UART DMAs arm64: dts: rockchip: enable DP for rk3399-gru arm64: dts: rockchip: add cdn-dp node for rk3399. arm64: dts: rockchip: add i2s0-2ch-bus pins on rk3399 arm64: dts: rockchip: enable tsadc on rk3399-puma arm64: dts: rockchip: add roc-rk3328-cc board arm64: dts: rockchip: Add cif test clocks for rk3399
| | * arm64: dts: rockchip: remove keep-power-in-suspend from sdhci of rk3399-sapphireShawn Lin2018-03-131-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | sdhci for rk3399-sapphire works for eMMC but keep-power-in-suspend is an optional property for SDIO. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * arm64: dts: rockchip: assign clock rate for ACLK_VIO on rk3399Shunqian Zheng2018-03-122-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ACLK_VIO is a parent clock used by a several children, its suggested clock rate is 400MHz. Right now it gets 400MHz because it sources from CPLL(800M) and divides by 2 after reset. It's good not to rely on default values like this, so let's explicitly set it. NOTE: it's expected that at least one board may override cru node and set the CPLL to 1.6 GHz. On that board it will be very important to be explicit about aclk-vio being 400 MHz. Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * arm64: dts: rockchip: add a standalone version of the rk3399 sapphireHeiko Stuebner2018-02-202-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While the sapphire board is a system-on-module and mostly used with the excavator baseboard, it is also possible to use it standalone without any base. So add a board-variant for this type. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Vicente Bergas <vicencb@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org>
| | * arm64: dts: rockchip: move rk3399-sapphire pwr_btn to daughterboardVicente Bergas2018-02-202-23/+23
| | | | | | | | | | | | | | | | | | | | | The power button is located on the daughterboard. Signed-off-by: Vicente Bergas <vicencb@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * arm64: dts: rockchip: move rk3399-sapphire i2s2 to daughterboardVicente Bergas2018-02-202-5/+5
| | | | | | | | | | | | | | | | | | | | | The i2s2 drives the HDMI audio, which has the connector on the daughterboard. Signed-off-by: Vicente Bergas <vicencb@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * arm64: dts: rockchip: move rk3399-sapphire sdio to excavator baseboardHeiko Stuebner2018-02-202-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | The sdio signals are routed through the connector to the baseboard, where the wifi module is also located. So move the sdio node to the excavator as well. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Vicente Bergas <vicencb@gmail.com>
| | * arm64: dts: rockchip: enable I2S codec on rk3399-puma-haikouKlaus Goger2018-02-192-0/+77
| | | | | | | | | | | | | | | | | | | | | | | | Enable the NXP SGTL5000 audio codec on the RK3399-Q7 EVK baseboard Haikou. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * arm64: dts: rockchip: move i2s0 node from baseboard to SoM on rk3399-pumaKlaus Goger2018-02-192-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | The I2S definition is part of the SoM and therefore should be in rk3399-puma.dtsi. Also correct the number of channels available. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * arm64: dts: rockchip: vdd_log on rk3399-sapphire is not an i2c slaveVicente Bergas2018-02-191-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | The vdd_log power supply is controlled by a PWM pin, not by i2c register access. There is a boot message that reports an error about not being able to bring that supply up. Signed-off-by: Vicente Bergas <vicencb@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * arm64: dts: rockchip: add Haikou baseboard with RK3368-uQ7 SoMKlaus Goger2018-02-172-0/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | Haikou is a Qseven and μQseven baseboard used in Theobroma Systems evaluation kits. This dts adds a version for use with a RK3368-uQ7 SoM called Lion. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * arm64: dts: rockchip: add RK3368-uQ7 (Lion) SoMKlaus Goger2018-02-171-0/+317
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RK3368-uQ7 SoM is a uQseven-compatible (40mm x 70mm, MXM-230 connector) system-on-module from Theobroma Systems, featuring the Rockchip RK3368. It provides the following feature set: * up to 4GB DDR3 * on-module SPI-NOR flash * on-module eMMC (with 8-bit 1.8V interface) * SD card (on a baseboad) via edge connector * Gigabit Ethernet with on-module Micrel KSZ9031 GbE PHY * HDMI/eDP/MIPI-DSI/LVDS * MIPI-CSI * USB - 1x USB 2.0 dual-role - 1x USB 2.0 host * on-module STM32 Cortex-M0 companion controller, implementing: - low-power RTC functionality (ISL1208 emulation) - fan controller (AMC6821 emulation) - USB<->CAN bridge controller Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * arm64: dts: rockchip: Fix RK3328 UART DMAsRobin Murphy2018-02-161-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using a serial console on RK3328 provokes an error from of_dma_request_slave_channel() since the UART nodes have a "dmas" property but are missing the mandatory "dma-names" to go with it. Replace the bogus "#dma-cells" - these UARTs are DMA channel consumers, not providers - with the appropriate names instead. DMA still doesn't actually work, since the PL330 driver doesn't quite implement everything the 8250 driver demands, but at least it makes the DT correct. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * arm64: dts: rockchip: enable DP for rk3399-gruChris Zhong2018-02-141-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable cdn_dp and create a cdn-dp-sound for the DP audio. Delete the endpoints between dp and vopL for gru, since we want the DP only use VOP big, which can support 4K mode. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> [dropped vop-hacks] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * arm64: dts: rockchip: add cdn-dp node for rk3399.Chris Zhong2018-02-141-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a node for the cdn DP controller which is embedded in the rk3399 SoC. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> [fixed whitespaces instead of tabs, dropped unnecessary address+size-cells and fixed the number of interrupt cells] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * arm64: dts: rockchip: add i2s0-2ch-bus pins on rk3399Klaus Goger2018-02-121-0/+10
| | | | | | | | | | | | | | | | | | | | | Add pin definition for I2S0 if used as a 2-channel only bus. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * arm64: dts: rockchip: enable tsadc on rk3399-pumaKlaus Goger2018-02-121-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the SoC thermal sensor on RK3399-Q7 (Puma). As we want to do do a full board reset instead of just a SoC one, set hw-tshut-mode to GPIO. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * arm64: dts: rockchip: add roc-rk3328-cc boardLevin Du2018-02-122-0/+268
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The roc-rk3328-cc is a credit card size single board computer using the Rockchip RK3328 Quad-Core ARM Cortex A53 64-Bit Processor and supporting up to 2GB 2133MHz LPDDR4 memory. It provides eMMC module socket, MicroSD Card slot, USB 2.0/3.0, Gigabit Ethernet, HDMI/CVBS, Infrared Receiver, SPDIF/I2S, and SPI/I2C/UART/PWM interfaces. The devicetree currently supports basic peripherals. Signed-off-by: Levin Du <djw@t-chip.com.cn> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * arm64: dts: rockchip: Add cif test clocks for rk3399Shunqian Zheng2018-02-121-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are three pins can act as cif test clock for rk3399. They're sourced from 24M and output 24M by default and some boards may use them as camera 24M xvclk. Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | | Revert "arm64: dts: rockchip: add usb3-phy otg-port support for rk3399"Heiko Stuebner2018-03-021-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit c301b327aea898af558b2387252a2f5fc0117dee. While this works splendidly on rk3399-gru devices using the cros-ec extcon, other rk3399-based devices using the fusb302 or no power-delivery controller at all don't probe at all anymore, as the typec-phy currently always expects the extcon to be available and therefore defers probing indefinitly on these. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | | arm64: dts: rockchip: Fix rk3399-gru-* s2r (pinctrl hogs, wifi reset)Douglas Anderson2018-03-011-13/+3Star
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Back in the early days when gru devices were still under development we found an issue where the WiFi reset line needed to be configured as early as possible during the boot process to avoid the WiFi module being in a bad state. We found that the way to get the kernel to do this in the earliest possible place was to configure this line in the pinctrl hogs, so that's what we did. For some history here you can see <http://crosreview.com/368770>. After the time that change landed in the kernel, we landed a firmware change to configure this line even earlier. See <http://crosreview.com/399919>. However, even after the firmware change landed we kept the kernel change to deal with the fact that some people working on devices might take a little while to update their firmware. At this there are definitely zero devices out in the wild that have firmware without the fix in it. Specifically looking in the firmware branch several critically important fixes for memory stability landed after the patch in coreboot and I know we didn't ship without those. Thus, by now, everyone should have the new firmware and it's safe to not have the kernel set this up in a pinctrl hog. Historically, even though it wasn't needed to have this in a pinctrl hog, we still kept it since it didn't hurt. Pinctrl would apply the default hog at bootup and then would never touch things again. That all changed with commit 981ed1bfbc6c ("pinctrl: Really force states during suspend/resume"). After that commit then we'll re-apply the default hog at resume time and that can screw up the reset state of WiFi. ...and on rk3399 if you touch a device on PCIe in the wrong way then the whole system can go haywire. That's what was happening. Specifically you'd resume a rk3399-gru-* device and it would mostly resume, then would crash with some crazy weird crash. One could say, perhaps, that the recent pinctrl change was at fault (and should be fixed) since it changed behavior. ...but that's not really true. The device tree for rk3399-gru is really to blame. Specifically since the pinctrl is defined in the hog and not in the "wlan-pd-n" node then the actual user of this pin doesn't have a pinctrl entry for it. That's bad. Let's fix our problems by just moving the control of "wlan_module_reset_l pinctrl" out of the hog and put them in the proper place. NOTE: in theory, I think it should actually be possible to have a pin controlled _both_ by the hog and by an actual device. Once the device claims the pin I think the hog is supposed to let go. I'm not 100% sure that this works and in any case this solution would be more complex than is necessary. Reported-by: Marc Zyngier <marc.zyngier@arm.com> Fixes: 48f4d9796d99 ("arm64: dts: rockchip: add Gru/Kevin DTS") Fixes: 981ed1bfbc6c ("pinctrl: Really force states during suspend/resume") Signed-off-by: Douglas Anderson <dianders@chromium.org> Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Tested-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | arm64: dts: rockchip: Fix DWMMC clocksRobin Murphy2018-02-162-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Trying to boot an RK3328 box with an HS200-capable eMMC, I see said eMMC fail to initialise as it can't run its tuning procedure, because the sample clock is missing. Upon closer inspection, whilst the clock is present in the DT, its name is subtly incorrect per the binding, so __of_clk_get_by_name() never finds it. By inspection, the drive clock suffers from a similar problem, so has never worked properly either. Fix up all instances of the incorrect clock names across the 64-bit DTs. Fixes: d717f7352ec6 ("arm64: dts: rockchip: add sdmmc/sdio/emmc nodes for RK3328 SoCs") Fixes: b790c2cab5ca ("arm64: dts: add Rockchip rk3368 core dtsi and board dts for the r88 board") Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | arm64: dts: rockchip: introduce pclk_vio_grf in rk3399-eDP device nodeYakir Yang2018-02-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pclk_vio_grf supply power for VIO GRF IOs, if it is disabled, driver would failed to operate the VIO GRF registers. The clock is optional but one of the side effects of don't have this clk is that the Samsung Chromebook Plus fails to recover display after a suspend/resume with following errors: rockchip-dp ff970000.edp: Input stream clock not detected. rockchip-dp ff970000.edp: Timeout of video streamclk ok rockchip-dp ff970000.edp: unable to config video Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> [this should also fix display failures when building rockchip-drm as module] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | arm64: dts: rockchip: correct ep-gpios for rk3399-sapphireShawn Lin2018-02-121-1/+1
| | | | | | | | | | | | | | | | The endpoint control gpio for rk3399-sapphire boards is gpio2_a4, so correct it now. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | arm64: dts: rockchip: fix rock64 gmac2io stability issuesKamil Trzciński2018-02-121-4/+3Star
|/ | | | | | | | | | | | | | | This commit enables thresh dma mode as this forces to disable checksuming, and chooses delay values which make the interface stable. These changes are needed, because ROCK64 is faced with two problems: 1. tx checksuming does not work with packets larger than 1498, 2. the default delays for tx/rx are not stable when using 1Gbps connection. Delays were found out with: https://github.com/ayufan-rock64/linux-build/tree/master/recipes/gmac-delays-test Signed-off-by: Kamil Trzciński <ayufan@ayufan.eu> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* Merge tag 'armsoc-dt' of ↵Linus Torvalds2018-02-024-9/+194
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC device tree updates from Arnd Bergmann: "We get a moderate number of new machines this time, and only one new SoC variant (Actions S700): Actions: - S700 Soc and CubieBoard7 development board - Allo.com Sparky Single-board-computer Allwinner: - Orange Pi R1 development board - Libre Computer Board ALL-H3-CC H3 single-board computer ASpeed ast2x00: - Witherspoon: OpenPower Power9 server manufactured by IBM that uses the ASPEED ast2500 - Zaius: OpenPower Power9 server manufactured by Invatech that uses the ASPEED ast2500 - Q71L: Intel Xeon server manufactured by Qanta that uses the ASPEED ast2400 AT91: - Axentia Nattis/Natte digital signage - sama5d2 PTC-ek Evaluation board Freescale/NXP i.MX: - SolidRun Humminboard2 development board - Variscite DART-MX6 SoM and Carrier-board - Technologic TS-4600 and TS-7970 development board - Toradex Colibri iMX7D SoM board - v1.5 variant of Solidrun Cubox-i and Hummingboard Freescale/NXP Layerscape: - Moxa UC-8410A Series industrial computer Gemini: - D-Link DNS-313 NAS enclosure OMAP: - LogicPD OMAP35xx SOM-LV devkit - LogicPD OMAP35xx Torpedo devkit Renesas: - r8a77970 (V3M) Starter Kit board - r8a7795 (M3-W) Salvator-XS board We finally managed to get the dtc warnings under control, with no more build-time warnings for bad device tree files. This includes fixes for the majority of platforms, including nomadik, samsung, lpc32xx, STi, spear, mediatek, freescale, qcom, realview, keystone, omap, kirkwood, renesas, hisilicon, and broadcom. Files get rearranged on a few platforms, in particular the Marvell Armada 7K/8K device tree files are changed in preparation for future SoC support, based on more than two of the same chips in one package, and some boards get renamed for oxnas for consistency. Finally, many existing SoCs gain descriptions for additional on-chip devices that we can now support with kernel drivers: - Allwinner A83t (drm, ethernet, i2c, ...), H3/H5 (USB-OTG) - Amlogic AXG family (clk, pinctrl, pwm, ...), and others (vpu, hdmi) - Aspeed clk controller support - Freescale LS1088A, LS1021A device support - Gemini Ethernet, PCI, TVE, panel - Keystone gpio, qspi, more uarts - Mediatek cpufreq, regulator, clock, reset - Marvell thermal, cpufreq, nand - Renesas SMP, thermal, timer, PWM, sound, phy, ipmmu - Rockchip Mipi, GPU, display - Samsung Exynos5433 PMU, power domain, nfc - Spreadtrum: sc9860 clocks - Tegra TX2 PSDI, HDMI, I2C,SMMU, display, fuse, ..." * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (690 commits) arm64: dts: stratix10: fix SPI settings ARM: dts: socfpga: add i2c reset signals arm64: dts: stratix10: add USB ECC reset bit arm64: dts: stratix10: enable USB on the devkit ARM: dts: socfpga: disable over-current for Arria10 USB devkit ARM: dts: Nokia N9: add support for up/down keys in the dts ARM: dts: nomadik: add interrupt-parent for clcd ARM: dts: Add ethernet to a bunch of platforms ARM: dts: Add ethernet to the Gemini SoC ARM: dts: rename oxnas dts files ARM: dts: s5pv210: add interrupt-parent for ohci ARM: lpc3250: fix uda1380 gpio numbers ARM: dts: STi: Add gpio polarity for "hdmi,hpd-gpio" property ARM: dts: dra7: Reduce shut down temperature of non-cpu thermal zones ARM: dts: n900: Add aliases for lcd and tvout displays ARM: dts: Update ti-sysc data for existing users ARM: dts: Fix smartreflex compatible for omap3 shared mpu-iva instance arm64: dts: marvell: armada-80x0: Fix pinctrl compatible string arm: spear13xx: Fix spics gpio controller's warning arm: spear13xx: Fix dmas cells ...
| * arm64: dts: rockchip: Add efuse device node for RK3328 SoCFinley Xiao2017-12-201-0/+25
| | | | | | | | | | | | | | This patch adds an efuse node in the device tree for rk3228 SoC. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * arm64: dts: rockchip: add rk3328 mali gpu nodeHeiko Stuebner2017-12-161-0/+22
| | | | | | | | | | | | | | Add the core gpu node for the rk3328, a Mali450MP2. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Rob Herring <robh@kernel.org>
| * arm64: dts: rockchip: add extcon nodes and enable tcphy rk3399-gruEnric Balletbo i Serra2017-12-161-0/+26
| | | | | | | | | | | | | | | | Enable tcphy and create the cros-ec's extcon node for the USB Type-C port. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * arm64: dts: rockchip: add usb3-phy otg-port support for rk3399Enric Balletbo i Serra2017-12-161-4/+4
| | | | | | | | | | | | | | Add the usb3 phyter for the USB3.0 OTG controller. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * arm64: dts: rockchip: add reset property for dwc3 controllers on rk3399Enric Balletbo i Serra2017-12-161-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After commit '06c47e6286d usb: dwc3: of-simple: Add support to get resets for the device' you can add the reset property to the dwc3 node, the reset is required for the controller to work properly, otherwise bind / unbind stress testing of the USB controller on rk3399 we'd often end up with lots of failures that looked like this: phy phy-ff800000.phy.9: phy poweron failed --> -110 dwc3 fe900000.dwc3: failed to initialize core dwc3: probe of fe900000.dwc3 failed with error -110 Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * arm64: dts: rockchip: add the aclk_usb3 clocks for USB3 on rk3399Enric Balletbo i Serra2017-12-161-4/+8
| | | | | | | | | | | | | | The aclk_usb3 must be enabled to support USB3 for rk3399. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * arm64: dts: rockchip: add pd_usb3 power-domain node for rk3399Enric Balletbo i Serra2017-12-161-0/+8
| | | | | | | | | | | | | | | | Add the usb3 power-domain, its qos area and assign it to the usb device node. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * arm64: dts: rockchip: Enable edp disaplay on kevinJeffy Chen2017-12-042-0/+45
| | | | | | | | | | | | | | | | | | Add edp panel and enable related nodes on kevin. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Reviewed-by: Mark Yao <mark.yao@rock-chips.com> Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * arm64: dts: rockchip: update mipi cells for RK3399Nickey Yang2017-12-041-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | We might include additional ports in derivative device trees, so the 'port' node should have an address, and the parent 'ports' node needs /#{addres,size}-cells. Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * arm64: dts: rockchip: add mipi_dsi1 support for rk3399Nickey Yang2017-12-041-0/+45
| | | | | | | | | | | | | | | | | | | | This patch adds the information for the secondary MIPI DSI controller, e.g., interrupts, grf, clocks, ports and so on. Mirrors the existing definition for dsi0. Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * arm64: dts: rockchip: add rk3399 DSI0 resetBrian Norris2017-12-041-0/+2
| | | | | | | | | | | | | | | | We've documented this one already, but we didn't add it to the DTSI yet. Suggested-by: Nickey Yang <nickey.yang@rock-chips.com> Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | arm64: dts: rockchip: limit rk3328-rock64 gmac speed to 100MBit for nowHeiko Stuebner2017-12-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | It looks like either the current kernel or the hardware has reliability issues when the gmac is actually running at 1GBit. In my test-case it is not able to boot on a nfsroot at this speed, as the system will always lose the connection to the nfs-server during boot, before reaching any login prompt and not recover from this. So until this is solved, limit the speed to 100MBit as with this the nfsroot survives stress tests like an apt-get upgrade without problems. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-19 18:03:51 +0200