summaryrefslogtreecommitdiffstats
path: root/arch/mips/include/asm/cpu-features.h
Commit message (Expand)AuthorAgeFilesLines
* MIPS: MemoryMapID (MMID) SupportPaul Burton2019-02-041-0/+13
* MIPS: Hardcode cpu_has_mips* where target ISA allowsPaul Burton2018-11-271-11/+24
* MIPS: Use Kconfig to select CPU_NO_EFFICIENT_FFSPaul Burton2018-11-121-10/+0Star
* MIPS: Hardcode cpu_has_fpu=0 when CONFIG_MIPS_FP_SUPPORT=nPaul Burton2018-11-091-3/+8
* MIPS: Hardcode cpu_has_mmips=1 for microMIPS kernelsPaul Burton2018-11-081-1/+3
* MIPS: Hardcode cpu_has_* where known at compile time due to ISAPaul Burton2018-07-241-69/+107
* MIPS: perf: More robustly probe for the presence of per-tc countersMatt Redfearn2018-05-151-0/+7
* MIPS: cpu-features.h: Replace __mips_isa_rev with MIPS_ISA_REVMatt Redfearn2018-03-091-2/+3
* MIPS: Introduce cpu_tcache_line_sizeMatt Redfearn2017-08-081-0/+3
* MIPS: MIPS16e2: Identify ASE presenceMaciej W. Rozycki2017-07-051-0/+3
* MIPS: Add CPU shared FTLB feature detectionPaul Burton2017-06-291-0/+41
* MIPS: Probe guest MVHJames Hogan2017-03-281-0/+3
* MIPS: Probe guest CP0_UserLocalJames Hogan2017-03-281-0/+3
* MIPS: Add defs & probing of UFRJames Hogan2017-03-281-0/+4
* lib/GCD.c: use binary GCD algorithm instead of EuclideanZhaoxiu Zeng2016-05-211-0/+10
* MIPS: Add probing & defs for VZ & guest featuresJames Hogan2016-05-131-0/+98
* MIPS: Add perf counter featureJames Hogan2016-05-131-0/+4
* MIPS: Add defs & probing of [X]ContextConfigJames Hogan2016-05-131-0/+4
* MIPS: Add defs & probing of BadInstr[P] registersJames Hogan2016-05-131-0/+8
* MIPS: Add defs & probing of extended CP0_EBaseJames Hogan2016-05-131-0/+4
* MIPS: Separate XPA CPU feature into LPA and MVHJames Hogan2016-05-131-1/+7
* MIPS: Loongson-3: Fast TLB refill handlerHuacai Chen2016-05-131-0/+3
* MIPS: Detect DSP v3 supportZubair Lutfullah Kakakhel2016-05-131-0/+4
* MIPS: Detect MIPSr6 Virtual Processor supportPaul Burton2016-05-131-0/+4
* MIPS: Define the legacy-NaN and 2008-NaN featuresMaciej W. Rozycki2016-01-201-0/+7
* MIPS: Allow RIXI for 32-bit kernels on MIPS64Paul Burton2015-11-111-5/+1Star
* MIPS: cpu-features: Add cpu_has_ftlbJames Hogan2015-09-221-0/+3
* MIPS: Probe for small (1KiB) page supportJames Hogan2015-09-031-0/+4
* MIPS: R12000: Enable branch prediction global historyJoshua Kinard2015-06-211-0/+3
* Merge branch '4.0-fixes' into mips-for-linux-nextRalf Baechle2015-04-131-1/+35
|\
| * MIPS: Fix cpu_has_mips_r2_exec_hazard.Ralf Baechle2015-04-101-1/+32
| * MIPS: Add support for XPA.Steven J. Hill2015-03-191-0/+3
* | MIPS: Correct FP ISA requirementsMaciej W. Rozycki2015-04-081-2/+5
* | MIPS: Correct `nofpu' non-functionalityMaciej W. Rozycki2015-04-081-0/+1
* | MIPS: Add arch CDMM definitions and probingJames Hogan2015-03-311-0/+4
|/
* MIPS: Handle MIPS IV, V and R2 FPU instructions on MIPS R6 as wellMarkos Chandras2015-02-171-1/+2
* MIPS: Add LLB bit and related feature for the Config 5 CP0 registerMarkos Chandras2015-02-171-0/+3
* MIPS: kernel: proc: Add MIPS R6 support to /proc/cpuinfoMarkos Chandras2015-02-171-0/+3
* MIPS: asm: cpu: Add MIPSR6 ISA definitionsLeonid Yegoshin2015-02-171-4/+15
* MIPS: detect presence of the FRE & UFR bitsPaul Burton2014-11-241-0/+4
* MIPS: Use WSBH/DSBH/DSHD on Loongson 3AChen Jie2014-09-221-0/+10
* MIPS: detect presence of MAARsPaul Burton2014-08-021-0/+3
* MIPS: Add new option for unique RI/XI exceptionsLeonid Yegoshin2014-08-021-0/+3
* MIPS: cpu: Add new cpu option for Hardware Table Walker.Markos Chandras2014-08-021-0/+3
* MIPS: Don't use RI/XI with 32-bit kernels on 64-bit CPUsDavid Daney2014-05-301-1/+8
* MIPS: math-emu: Remove most ifdefery.Ralf Baechle2014-05-211-0/+11
* MIPS: asm: cpu: Add cpu flag for Enhanced Virtual AddressingMarkos Chandras2014-03-261-1/+3
* MIPS: Detect the MSA ASEPaul Burton2014-03-261-0/+6
* MIPS: features: Add initial support for Segmentation Control registersSteven J. Hill2014-01-221-0/+4
* MIPS: features: Add initial support for TLBINVF capable coresLeonid Yegoshin2014-01-221-0/+3
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-01 16:19:42 +0200