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path: root/arch/mips/include/asm/mipsregs.h
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* MIPS: Stop setting I6400 FTLBPPaul Burton2016-09-291-2/+0Star
* MIPS: Add define for Config.VI (virtual icache) bitJames Hogan2016-06-151-0/+1
* MIPS: Clean up RDHWR handlingJames Hogan2016-06-151-1/+19
* MIPS: Add 64-bit HTW fieldsJames Hogan2016-05-281-0/+8
* MIPS: Simplify DSP instruction encoding macrosJames Hogan2016-05-281-90/+17Star
* MIPS: Add missing tlbinvf/XPA microMIPS encodingsJames Hogan2016-05-281-5/+7
* MIPS: Add missing VZ accessor microMIPS encodingsJames Hogan2016-05-281-9/+18
* MIPS: Add inline asm encoding helpersJames Hogan2016-05-281-0/+27
* MIPS: Fix write_gc0_* macros when writing zeroJames Hogan2016-05-281-2/+2
* MIPS: Add definitions of SegCtl registers and use themMatt Redfearn2016-05-281-0/+3
* MIPS: Fix VZ probe gas errors with binutils <2.24James Hogan2016-05-171-180/+293
* MIPS: Add guest CP0 accessorsJames Hogan2016-05-131-11/+330
* MIPS: Add register definitions for VZ ASE registersJames Hogan2016-05-131-0/+117
* MIPS: Avoid magic numbers probing kscratch_maskJames Hogan2016-05-131-1/+2
* MIPS: Add defs & probing of [X]ContextConfigJames Hogan2016-05-131-0/+6
* MIPS: Add defs & probing of BadInstr[P] registersJames Hogan2016-05-131-0/+3
* MIPS: Add defs & probing of extended CP0_EBaseJames Hogan2016-05-131-0/+3
* MIPS: Define & use CP0_EBase bit definitionsJames Hogan2016-05-131-1/+9
* MIPS: Add & use CP0_EntryHi ASID definitionsJames Hogan2016-05-131-0/+2
* MIPS: Loongson-3: Fast TLB refill handlerHuacai Chen2016-05-131-0/+6
* MIPS: Loongson: Invalidate special TLBs when neededHuacai Chen2016-05-131-0/+9
* MIPS: Loongson: Add Loongson-3A R2 basic supportHuacai Chen2016-05-131-0/+2
* MIPS: Add and use watch register field definitionsJames Hogan2016-05-131-0/+18
* MIPS: Add and use CAUSEF_WP definitionJames Hogan2016-05-131-0/+2
* MIPS: Detect MIPSr6 Virtual Processor supportPaul Burton2016-05-131-0/+1
* MIPS: Update trap codesJames Hogan2016-01-241-2/+10
* MIPS: Move Cause.ExcCode trap codes to mipsregs.hJames Hogan2016-01-241-0/+24
* MIPS: Move definition of DC bit to mipsregs.hJames Hogan2016-01-241-0/+2
* MIPS: Tidy EntryLo bit definitions, add PFNPaul Burton2015-11-111-9/+3Star
* MIPS: CPS: Early debug using an ns16550-compatible UARTPaul Burton2015-11-111-0/+3
* MIPS: Fix duplicate CP0_* definitions.James Hogan2015-11-111-0/+3
* MIPS: cpu-features: Add cpu_has_ftlbJames Hogan2015-09-221-0/+2
* MIPS: Rearrange ENTRYLO field definitionsJames Hogan2015-09-031-25/+27
* MIPS: Treat CP1 control registers as unsigned ints.Ralf Baechle2015-09-031-1/+1
* MIPS: Use unsigned int when reading CP0 registersChris Packham2015-09-031-2/+2
* MIPS: Set up FTLB probability for I6400Markos Chandras2015-08-261-0/+2
* MIPS: R12000: Enable branch prediction global historyJoshua Kinard2015-06-211-0/+13
* MIPS: mipsregs.h: Add EntryLo bit definitionsJames Hogan2015-06-211-0/+22
* MIPS: math-emu: Define IEEE 754-2008 feature control bitsMaciej W. Rozycki2015-04-081-2/+7
* MIPS: math-emu: Implement the FCCR, FEXR and FENR registersMaciej W. Rozycki2015-04-081-12/+57
* MIPS: mipsregs.h: Reindent CP0 Cause macrosMaciej W. Rozycki2015-04-081-16/+16
* MIPS: mipsregs.h: Move TX39 macros out of the wayMaciej W. Rozycki2015-04-081-33/+33
* MIPS: mipsregs.h: Reorder CP1 macro definitionsMaciej W. Rozycki2015-04-081-72/+75
* MIPS: mipsregs.h: Remove broken commentsMaciej W. Rozycki2015-04-081-6/+0Star
* MIPS: Add architectural FDC IRQ fieldsJames Hogan2015-03-311-0/+4
* MIPS: Add arch CDMM definitions and probingJames Hogan2015-03-311-0/+11
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2015-02-221-0/+4
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| * MIPS: Add set/clear CP0 macros for PageGrain registerSteven J. Hill2015-02-201-0/+1
| * MIPS: asm: mipsregs: Add support for the LLADDR registerMarkos Chandras2015-02-171-0/+2
| * MIPS: Add LLB bit and related feature for the Config 5 CP0 registerMarkos Chandras2015-02-171-0/+1
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