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* riscv: rename SR_* constants to match the specChristoph Hellwig2018-01-083-10/+10
* riscv: remove CONFIG_MMU ifdefsChristoph Hellwig2018-01-084-24/+0Star
* RISC-V: Make __NR_riscv_flush_icache visible to userspacePalmer Dabbelt2018-01-083-28/+27Star
* RISC-V: Resurrect smp_mb__after_spinlock()Palmer Dabbelt2017-12-111-0/+19
* bpf: correct broken uapi for BPF_PROG_TYPE_PERF_EVENT program typeHendrik Brueckner2017-12-051-0/+1
* RISC-V: Fixes for clean allmodconfig buildPalmer Dabbelt2017-12-016-17/+22
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| * RISC-V: Add missing includeOlof Johansson2017-11-301-0/+1
| * RISC-V: Use define for get_cycles like other architecturesOlof Johansson2017-11-301-1/+2
| * RISC-V: io.h: type fixes for warningsOlof Johansson2017-11-301-7/+9
| * RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macrosOlof Johansson2017-11-302-9/+9
| * RISC-V: use generic serial.hOlof Johansson2017-11-301-0/+1
* | RISC-V: __io_writes should respect the length argumentPalmer Dabbelt2017-12-011-1/+1
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| * | RISC-V: __io_writes should respect the length argumentPalmer Dabbelt2017-12-011-1/+1
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* | RISC-V: User-Visible ChangesPalmer Dabbelt2017-12-017-30/+140
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| * | RISC-V: Allow userspace to flush the instruction cacheAndrew Waterman2017-11-303-0/+38
| * | RISC-V: Flush I$ when making a dirty page executableAndrew Waterman2017-11-305-30/+102
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* | RISC-V: remove spin_unlock_wait()Palmer Dabbelt2017-11-281-9/+0Star
* | RISC-V: `sfence.vma` orderes the instruction cachePalmer Dabbelt2017-11-281-1/+4
* | RISC-V: Add READ_ONCE in arch_spin_is_locked()Palmer Dabbelt2017-11-281-1/+1
* | RISC-V: __test_and_op_bit_ord should be strongly orderedPalmer Dabbelt2017-11-281-1/+1
* | RISC-V: Remove smb_mb__{before,after}_spinlock()Palmer Dabbelt2017-11-281-8/+0Star
* | RISC-V: Remove __smp_bp__{before,after}_atomicPalmer Dabbelt2017-11-281-15/+0Star
* | RISC-V: Comment on why {,cmp}xchg is ordered how it isPalmer Dabbelt2017-11-281-2/+7
* | RISC-V: Remove unused arguments from ATOMIC_OPPalmer Dabbelt2017-11-281-47/+47
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* Merge tag 'riscv-for-linus-4.15-arch-v9-premerge' of git://git.kernel.org/pub...Linus Torvalds2017-11-151-14/+0Star
* RISC-V: Build InfrastructurePalmer Dabbelt2017-09-271-0/+61
* RISC-V: User-facing APIPalmer Dabbelt2017-09-2715-0/+710
* RISC-V: Paging and MMUPalmer Dabbelt2017-09-277-0/+910
* RISC-V: Device, timer, IRQs, and the SBIPalmer Dabbelt2017-09-277-0/+364
* RISC-V: Task implementationPalmer Dabbelt2017-09-276-0/+328
* RISC-V: ELF and module implementationPalmer Dabbelt2017-09-273-0/+150
* RISC-V: Generic library routines and assemblyPalmer Dabbelt2017-09-276-0/+822
* RISC-V: Atomic and Locking CodePalmer Dabbelt2017-09-2710-0/+1423
* RISC-V: Init and Halt CodePalmer Dabbelt2017-09-273-0/+162
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