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* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner2019-06-051-9/+1Star
* RISC-V: Access CSRs using CSR numbersAnup Patel2019-05-171-11/+11
* RISC-V: Add _TIF_NEED_RESCHED check for kernel thread when CONFIG_PREEMPT=yVincent Chen2019-01-231-1/+17
* riscv: add audit supportDavid Abdurachmanov2019-01-071-2/+2
* RISC-V: SMP cleanup and new featuresPalmer Dabbelt2018-10-231-1/+0Star
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| * RISC-V: No need to pass scause as arg to do_IRQ()Anup Patel2018-10-231-1/+0Star
* | Extract FPU context operations from entry.SAlan Kao2018-10-231-87/+0Star
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* RISC-V: implement low-level interrupt handlingChristoph Hellwig2018-08-131-2/+2
* RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handlerPalmer Dabbelt2018-03-141-4/+3Star
* RISC-V: Enable IRQ during exception handlingzongbox@gmail.com2018-02-201-2/+3
* riscv: disable SUM in the exception handlerChristoph Hellwig2018-01-311-3/+6
* riscv: rename SR_* constants to match the specChristoph Hellwig2018-01-081-4/+4
* RISC-V: Task implementationPalmer Dabbelt2017-09-271-0/+464
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