summaryrefslogtreecommitdiffstats
path: root/arch/riscv
Commit message (Expand)AuthorAgeFilesLines
* RISC-V: refresh defconfigAnup Patel2018-11-021-8/+8
* Merge tag 'riscv-for-linus-4.20-mw2' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2018-11-013-7/+5Star
|\
| * lib: Remove umoddi3 and udivmoddi4Palmer Dabbelt2018-10-311-1/+0Star
| |\
| | * Revert "RISC-V: Select GENERIC_LIB_UMODDI3 on RV32"Palmer Dabbelt2018-10-311-1/+0Star
| * | Move EM_RISCV into elf-em.hPalmer Dabbelt2018-10-311-3/+0Star
| * | RISC-V: properly determine hardware capsAndreas Schwab2018-10-311-3/+5
| |/
* | mm: remove include/linux/bootmem.hMike Rapoport2018-10-311-2/+1Star
* | memblock: rename free_all_bootmem to memblock_free_allMike Rapoport2018-10-311-1/+1
* | mm: remove CONFIG_HAVE_MEMBLOCKMike Rapoport2018-10-311-1/+0Star
* | mm: remove CONFIG_NO_BOOTMEMMike Rapoport2018-10-311-1/+0Star
* | treewide: remove current_text_addrNick Desaulniers2018-10-311-6/+0Star
* | Merge tag 'riscv-for-linus-4.20-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2018-10-2627-238/+679
|\|
| * RISC-V: SMP cleanup and new featuresPalmer Dabbelt2018-10-2310-62/+245
| |\
| | * RISC-V: Show IPI statsAnup Patel2018-10-233-7/+49
| | * RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfoAnup Patel2018-10-231-4/+6
| | * RISC-V: Use Linux logical CPU number instead of hartidAtish Patra2018-10-236-25/+58
| | * RISC-V: Add logical CPU indexing for RISC-VAtish Patra2018-10-233-1/+46
| | * RISC-V: Use WRITE_ONCE instead of direct accessAtish Patra2018-10-231-2/+3
| | * RISC-V: Use mmgrab()Palmer Dabbelt2018-10-231-1/+2
| | * RISC-V: Rename im_okay_therefore_i_am to found_boot_cpuPalmer Dabbelt2018-10-231-4/+5
| | * RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartidPalmer Dabbelt2018-10-233-4/+7
| | * RISC-V: Provide a cleaner raw_smp_processor_id()Palmer Dabbelt2018-10-231-10/+4Star
| | * RISC-V: Disable preemption before enabling interruptsAtish Patra2018-10-231-1/+5
| | * RISC-V: Comment on the TLB flush in smp_callin()Palmer Dabbelt2018-10-231-0/+4
| | * RISC-V: Filter ISA and MMU values in cpuinfoPalmer Dabbelt2018-10-231-7/+61
| | * RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}Palmer Dabbelt2018-10-231-7/+0Star
| | * RISC-V: No need to pass scause as arg to do_IRQ()Anup Patel2018-10-232-3/+2Star
| * | RISC-V: Fix some RV32 bugs and build failuresPalmer Dabbelt2018-10-234-2/+7
| |\ \
| | * | RISC-V: Avoid corrupting the upper 32-bit of phys_addr_t in ioremapVincent Chen2018-10-231-1/+1
| | * | RISC-V: Select GENERIC_LIB_UMODDI3 on RV32Zong Li2018-10-231-0/+1
| | * | RISC-V: Use swiotlb on RV64 onlyZong Li2018-10-231-0/+3
| | * | RISC-V: Build tishift only on 64-bitZong Li2018-10-231-1/+2
| | |/
| * | riscv: Add support to no-FPU systemsPalmer Dabbelt2018-10-239-127/+196
| |\ \
| | * | Auto-detect whether a FPU existsAlan Kao2018-10-234-7/+19
| | * | Allow to disable FPU supportAlan Kao2018-10-236-3/+29
| | * | Cleanup ISA string settingAlan Kao2018-10-231-11/+8Star
| | * | Refactor FPU code in signal setup/return proceduresAlan Kao2018-10-231-27/+41
| | * | Extract FPU context operations from entry.SAlan Kao2018-10-233-87/+107
| | |/
| * | RISC-V: Cosmetic menuconfig changesNick Kossifidis2018-10-232-36/+39
| * | riscv: move GCC version check for ARCH_SUPPORTS_INT128 to KconfigMasahiro Yamada2018-10-232-2/+1Star
| * | RISC-V: remove the unused return_to_handler exportChristoph Hellwig2018-10-231-1/+0Star
| * | RISC-V: Add futex support.Jim Wilson2018-10-233-1/+129
| * | RISC-V: Add FP register ptrace support for gdb.Jim Wilson2018-10-232-0/+55
| * | RISC-V: Mask out the F extension on systems without DPalmer Dabbelt2018-10-231-0/+7
| * | RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}Palmer Dabbelt2018-10-231-7/+0Star
| |/
* | Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2018-10-251-0/+1
|\ \
| * | RISC-V: Request newstat syscallsGuenter Roeck2018-09-051-0/+1
* | | Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...Linus Torvalds2018-10-242-24/+1Star
|\ \ \ | |_|/ |/| |
| * | signal: Remove the need for __ARCH_SI_PREABLE_SIZE and SI_PAD_SIZEEric W. Biederman2018-10-032-24/+1Star
| |/
* | RISCV: Fix end PFN for low memoryAtish Patra2018-10-021-1/+1
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-06-30 17:17:09 +0200