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path: root/drivers/clk/mediatek/clk-mt2701.c
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* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner2019-05-301-9/+1Star
* clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_selchunhui dai2019-02-251-2/+2
* clk: mediatek: remove unused array audio_parentsColin Ian King2018-08-311-5/+0Star
* clk: mediatek: correct the clocks for MT2701 HDMI PHY moduleRyder Lee2018-05-161-2/+6
* clk: mediatek: fix PWM clock source by adding a fixed-factor clockSean Wang2018-03-191-7/+8
* clk: mediatek: mark mtk_infrasys_init_early __initArnd Bergmann2017-11-021-1/+1
* clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCsSean Wang2017-06-201-0/+8
* reset: mediatek: Add MT2701 reset driverShunli Wang2016-11-091-2/+10
* clk: mediatek: Add MT2701 clock supportShunli Wang2016-11-091-0/+1027