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path: root/drivers/clk/meson/axg.c
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* clk: meson: axg: spread spectrum is on mpll2Jerome Brunet2019-05-201-5/+5
* clk: meson: factorise meson64 peripheral clock controller driversJerome Brunet2019-02-041-49/+10Star
* clk: meson: rework and clean drivers dependenciesJerome Brunet2019-02-021-1/+4
* clk: meson: axg: claim clock controller input clock from DTJerome Brunet2019-01-181-8/+19
* clk: meson: axg: mark fdiv2 and fdiv3 as criticalJerome Brunet2018-11-081-0/+13
* clk: meson-axg: pcie: drop the mpll3 clock parentYixun Lan2018-09-261-2/+4
* clk: meson: clk-pll: drop hard-coded rates from pll tablesJerome Brunet2018-09-261-37/+36Star
* clk: meson: clk-pll: remove od parametersJerome Brunet2018-09-261-130/+154
* clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessaryJerome Brunet2018-09-261-1/+0Star
* clk: meson: clk-pll: add enable bitJerome Brunet2018-09-261-3/+25
* clk: meson: add gen_clkJerome Brunet2018-07-091-1/+63
* clk: meson-axg: add clocks required by pcie driverYixun Lan2018-07-091-0/+145
* clk: meson: remove obsolete register accessJerome Brunet2018-07-091-35/+2Star
* clk: meson: axg: let mpll clocks round closestJerome Brunet2018-05-211-0/+4
* clk: meson: Drop unused local variable and add staticStephen Boyd2018-03-141-2/+2
* clk: meson: add fdiv clock gatesJerome Brunet2018-03-131-10/+85
* clk: meson: add mpll pre-dividerJerome Brunet2018-03-131-4/+20
* clk: meson: axg: add hifi pll clockJerome Brunet2018-03-131-0/+55
* clk: meson: add gp0 frac parameter for axg and gxlJerome Brunet2018-03-131-1/+6
* clk: meson: remove special gp0 lock loopJerome Brunet2018-03-131-1/+0Star
* clk: meson: poke pll CNTL lastJerome Brunet2018-03-131-1/+1
* clk: meson: use hhi syscon if availableJerome Brunet2018-03-131-13/+30
* clk: meson: split divider and gate part of mpllJerome Brunet2018-03-131-28/+72
* clk: meson: migrate plls clocks to clk_regmapJerome Brunet2018-03-131-105/+108
* clk: meson: migrate mplls clocks to clk_regmapJerome Brunet2018-03-131-124/+121Star
* clk: meson: migrate muxes to clk_regmapJerome Brunet2018-03-131-35/+25Star
* clk: meson: migrate dividers to clk_regmapJerome Brunet2018-03-131-35/+26Star
* clk: meson: migrate gates to clk_regmapJerome Brunet2018-03-131-37/+35Star
* clk: meson: add regmap to the clock controllersJerome Brunet2018-03-131-1/+14
* clk: meson: remove obsolete commentsJerome Brunet2018-03-131-5/+0Star
* clk: meson: only one loop index is necessary in probeJerome Brunet2018-03-131-4/+4
* clk: meson: use devm_of_clk_add_hw_providerJerome Brunet2018-03-131-2/+2
* clk: meson: use dev pointer where possibleJerome Brunet2018-03-131-4/+4
* clk: meson: add axg misc bit to the mpll driverJerome Brunet2018-02-121-0/+20
* clk: meson: axg: fix the od shift of the sys_pllYixun Lan2018-02-121-1/+1
* clk: meson: axg: add the fractional part of the fixed_pllJerome Brunet2018-02-121-0/+5
* clk: meson: remove useless pll rate params tablesJerome Brunet2018-02-121-94/+0Star
* clk: meson-axg: fix potential NULL dereference in axg_clkc_probe()weiyongjun (A)2018-01-101-0/+2
* clk: meson-axg: make local symbol axg_gp0_params_table staticweiyongjun (A)2017-12-281-1/+1
* clk: meson-axg: fix return value check in axg_clkc_probe()weiyongjun (A)2017-12-281-1/+1
* clk: meson-axg: add clock controller driversQiufang Dai2017-12-141-0/+936
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