openslx/kernel-qcow2-linux.git - In-kernel qcow2 (Kernel part)

	Commit message (Expand)	Author	Age	Files	Lines
*	clk: meson: meson8b: add the video decoder clock trees	Martin Blumenstingl	2019-04-01	1	-1/+16
*	clk: meson: meson8b: add the VPU clock trees	Martin Blumenstingl	2019-04-01	1	-1/+8
*	clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2	Martin Blumenstingl	2019-04-01	1	-1/+4
*	clk: meson: meson8b: fix the naming of the APB clocks	Martin Blumenstingl	2019-02-13	1	-1/+1
*	clk: meson: meson8b: add the GPU clock tree	Martin Blumenstingl	2019-01-07	1	-1/+8
*	clk: meson: meson8b: add the read-only video clock trees	Martin Blumenstingl	2018-12-03	1	-2/+51
*	clk: meson: meson8b: add the fractional divider for vid_pll_dco	Martin Blumenstingl	2018-12-03	1	-0/+1
*	clk: meson: meson8b: add the CPU clock post divider clocks	Martin Blumenstingl	2018-11-23	1	-1/+12
*	clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3	Martin Blumenstingl	2018-11-23	1	-2/+2
*	clk: meson: clk-pll: remove od parameters	Jerome Brunet	2018-09-26	1	-1/+4
*	clk: meson: use SPDX license identifiers consistently	Jerome Brunet	2018-05-18	1	-12/+1
*	clk: meson: meson8b: add support for the NAND clocks	Martin Blumenstingl	2018-05-15	1	-1/+4
*	clk: meson: add fdiv clock gates	Jerome Brunet	2018-03-13	1	-1/+6
*	clk: meson: add mpll pre-divider	Jerome Brunet	2018-03-13	1	-1/+2
*	clk: meson: rework meson8b cpu clock	Jerome Brunet	2018-03-13	1	-1/+6
*	clk: meson: split divider and gate part of mpll	Jerome Brunet	2018-03-13	1	-1/+5
*	clk: meson: meson8b: register the built-in reset controller	Martin Blumenstingl	2017-08-04	1	-1/+8
*	clk: meson8b: expose every clock in the bindings	Jerome Brunet	2017-08-04	1	-99/+4
*	clk: meson8b: export the ethernet gate clock	Martin Blumenstingl	2017-06-12	1	-1/+1
*	clk: meson8b: export the USB clocks	Martin Blumenstingl	2017-06-12	1	-5/+5
*	clk: meson8b: export the gate clock for the HW random number generator	Martin Blumenstingl	2017-06-12	1	-1/+1
*	clk: meson8b: export the SDIO clock	Martin Blumenstingl	2017-06-12	1	-1/+1
*	clk: meson8b: export the SAR ADC clocks	Martin Blumenstingl	2017-06-12	1	-2/+2
*	clk: meson8b: add the mplls clocks 0, 1 and 2	Jerome Brunet	2017-03-27	1	-1/+19
*	meson: clk: Add support for clock gates	Alexander Müller	2016-09-02	1	-0/+5
*	clk: meson: Copy meson8b CLKID defines to private header file	Alexander Müller	2016-09-02	1	-0/+107
*	meson: clk: Rename register names according to Amlogic datasheet	Alexander Müller	2016-09-02	1	-6/+5
*	meson: clk: Move register definitions to meson8b.h	Alexander Müller	2016-09-02	1	-0/+40