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path: root/drivers/clk/meson
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* treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-212-0/+2
*---. Merge branches 'clk-doc', 'clk-more-critical', 'clk-meson' and 'clk-basic-be'...Stephen Boyd2019-05-079-516/+2171
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| | * | clk: meson: axg-audio: add g12a supportMaxime Jourdan2019-04-082-8/+239
| | * | clk: meson: axg-audio: don't register inputs in the onecell dataJerome Brunet2019-04-082-44/+6Star
| | * | clk: meson: axg_audio: replace prefix axg by audJerome Brunet2019-04-081-482/+482
| | * | clk: meson: meson8b: add the video decoder clock treesMartin Blumenstingl2019-04-012-1/+328
| | * | clk: meson: meson8b: add the VPU clock treesMartin Blumenstingl2019-04-012-1/+175
| | * | clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2Martin Blumenstingl2019-04-012-1/+66
| | * | clk: meson: meson8b: use a separate clock table for Meson8m2Martin Blumenstingl2019-04-011-1/+192
| | * | clk: meson-g12a: add video decoder clocksMaxime Jourdan2019-04-012-1/+170
| | * | clk: meson-g12a: add PCIE PLL clocksNeil Armstrong2019-04-012-1/+122
| | * | clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLLNeil Armstrong2019-04-012-0/+27
| | * | clk: meson: g12a: add cpu clocksNeil Armstrong2019-04-012-1/+371
| | * | dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCINNeil Armstrong2019-04-011-1/+0Star
| | * | dt-bindings: clock: axg-audio: unexpose controller inputsJerome Brunet2019-04-011-0/+20
| | * | clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock idNeil Armstrong2019-03-191-1/+0Star
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* | | clk: meson: vid-pll-div: remove warning and return 0 on invalid configNeil Armstrong2019-03-291-2/+2
* | | clk: meson: pll: fix rounding and setting a rate that matches preciselyMartin Blumenstingl2019-03-251-1/+1
* | | clk: meson-g12a: fix VPU clock parentsNeil Armstrong2019-03-191-1/+1
* | | clk: meson: g12a: fix VPU clock muxes maskMaxime Jourdan2019-03-191-2/+2
* | | clk: meson-gxbb: round the vdec dividers to closestMaxime Jourdan2019-03-191-0/+2
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* | clk: meson: meson8b: fix the naming of the APB clocksMartin Blumenstingl2019-02-132-14/+14
* | clk: meson: Add G12A AO Clock + Reset ControllerNeil Armstrong2019-02-134-1/+491
* | clk: meson: factorise meson64 peripheral clock controller driversJerome Brunet2019-02-047-176/+313
* | clk: meson: g12a: add peripheral clock controllerJian Hu2019-02-045-2/+2594
* | clk: meson: pll: update driver for the g12aJerome Brunet2019-02-042-59/+154
* | clk: meson: rework and clean drivers dependenciesJerome Brunet2019-02-0229-281/+465
* | clk: meson: axg-audio does not require sysconJerome Brunet2019-02-021-1/+1
* | clk: meson: ao-clkc: claim clock controller input clocks from DTJerome Brunet2019-01-184-14/+82
* | clk: meson: axg: claim clock controller input clock from DTJerome Brunet2019-01-181-8/+19
* | clk: meson: gxbb: claim clock controller input clock from DTJerome Brunet2019-01-181-13/+24
* | clk: meson: meson8b: add the GPU clock treeMartin Blumenstingl2019-01-072-1/+154
* | clk: meson: meson8b: use a separate clock table for Meson8Martin Blumenstingl2019-01-071-6/+197
* | clk: meson: axg-ao: add 32k generation subtreeJerome Brunet2019-01-072-25/+163
* | clk: meson: gxbb-ao: replace cec-32k with the dual dividerJerome Brunet2019-01-074-262/+204Star
* | clk: meson: add dual divider clock driverJerome Brunet2019-01-073-1/+150
* | clk: meson: clean-up clock registrationJerome Brunet2019-01-071-5/+10
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* Merge branch 'clk-fixes' into clk-nextStephen Boyd2018-12-142-0/+25
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| * clk: meson: axg: mark fdiv2 and fdiv3 as criticalJerome Brunet2018-11-081-0/+13
| * clk: meson-gxbb: set fclk_div3 as CLK_IS_CRITICALChristian Hewitt2018-11-081-0/+12
* | Merge tag 'meson-clk-4.21-2' of https://github.com/BayLibre/clk-meson into cl...Stephen Boyd2018-12-137-71/+870
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| * | clk: meson: axg-audio: use the clk input helper functionJerome Brunet2018-12-111-59/+24Star
| * | clk: meson: add clk-input helper functionJerome Brunet2018-12-053-0/+50
| * | clk: meson: meson8b: add the read-only video clock treesMartin Blumenstingl2018-12-032-10/+782
| * | clk: meson: meson8b: add the fractional divider for vid_pll_dcoMartin Blumenstingl2018-12-032-0/+6
| * | clk: meson: meson8b: fix the offset of vid_pll_dco's N valueMartin Blumenstingl2018-12-031-1/+1
| * | clk: meson: Fix GXL HDMI PLL fractional bits widthNeil Armstrong2018-11-271-1/+7
* | | clk: meson: Mark some things staticStephen Boyd2018-12-032-6/+6
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* | clk: meson: meson8b: add the CPU clock post divider clocksMartin Blumenstingl2018-11-232-1/+256
* | clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3Martin Blumenstingl2018-11-232-12/+12
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