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* | clk: meson: axg-ao: add 32k generation subtreeJerome Brunet2019-01-072-25/+163
* | clk: meson: gxbb-ao: replace cec-32k with the dual dividerJerome Brunet2019-01-074-262/+204Star
* | clk: meson: add dual divider clock driverJerome Brunet2019-01-073-1/+150
* | clk: meson: clean-up clock registrationJerome Brunet2019-01-071-5/+10
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* Merge branch 'clk-fixes' into clk-nextStephen Boyd2018-12-142-0/+25
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| * clk: meson: axg: mark fdiv2 and fdiv3 as criticalJerome Brunet2018-11-081-0/+13
| * clk: meson-gxbb: set fclk_div3 as CLK_IS_CRITICALChristian Hewitt2018-11-081-0/+12
* | Merge tag 'meson-clk-4.21-2' of https://github.com/BayLibre/clk-meson into cl...Stephen Boyd2018-12-137-71/+870
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| * | clk: meson: axg-audio: use the clk input helper functionJerome Brunet2018-12-111-59/+24Star
| * | clk: meson: add clk-input helper functionJerome Brunet2018-12-053-0/+50
| * | clk: meson: meson8b: add the read-only video clock treesMartin Blumenstingl2018-12-032-10/+782
| * | clk: meson: meson8b: add the fractional divider for vid_pll_dcoMartin Blumenstingl2018-12-032-0/+6
| * | clk: meson: meson8b: fix the offset of vid_pll_dco's N valueMartin Blumenstingl2018-12-031-1/+1
| * | clk: meson: Fix GXL HDMI PLL fractional bits widthNeil Armstrong2018-11-271-1/+7
* | | clk: meson: Mark some things staticStephen Boyd2018-12-032-6/+6
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* | clk: meson: meson8b: add the CPU clock post divider clocksMartin Blumenstingl2018-11-232-1/+256
* | clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3Martin Blumenstingl2018-11-232-12/+12
* | clk: meson: clk-regmap: add read-only gate opsMartin Blumenstingl2018-11-232-0/+6
* | clk: meson: meson8b: allow changing the CPU clock treeMartin Blumenstingl2018-11-231-6/+6
* | clk: meson: meson8b: run from the XTAL when changing the CPU frequencyMartin Blumenstingl2018-11-231-0/+63
* | clk: meson: meson8b: add support for more M/N values in sys_pllMartin Blumenstingl2018-11-231-0/+5
* | clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICALMartin Blumenstingl2018-11-231-1/+2
* | clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_selMartin Blumenstingl2018-11-231-2/+9
* | clk: meson: clk-pll: check if the clock is already enabledMartin Blumenstingl2018-11-231-0/+19
* | clk: meson: meson8b: fix the width of the cpu_scale_div clockMartin Blumenstingl2018-11-231-1/+1
* | clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_tableMartin Blumenstingl2018-11-231-7/+8
* | clk: meson: meson8b: use the HHI syscon if availableMartin Blumenstingl2018-11-231-9/+15
* | clk: meson-gxbb: Add video clocksNeil Armstrong2018-11-231-0/+722
* | dt-bindings: clk: meson-gxbb: Add Video clock bindingsNeil Armstrong2018-11-231-2/+24
* | clk: meson-gxbb: Fix HDMI PLL for GXL SoCsNeil Armstrong2018-11-231-2/+49
* | clk: meson: Add vid_pll divider driverNeil Armstrong2018-11-233-1/+98
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* clk: meson: meson8b: use the regmap in the internal reset controllerMartin Blumenstingl2018-09-261-7/+6Star
* clk: meson: meson8b: register the clock controller earlyMartin Blumenstingl2018-09-261-60/+34Star
* clk: meson-axg: pcie: drop the mpll3 clock parentYixun Lan2018-09-261-2/+4
* clk: meson: axg: round audio system master clocks downJerome Brunet2018-09-261-11/+23
* clk: meson: clk-pll: drop hard-coded rates from pll tablesJerome Brunet2018-09-265-142/+162
* clk: meson: clk-pll: remove od parametersJerome Brunet2018-09-268-498/+493Star
* clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessaryJerome Brunet2018-09-263-8/+8
* clk: meson: clk-pll: add enable bitJerome Brunet2018-09-265-10/+113
* clk: meson: add gen_clkJerome Brunet2018-07-094-3/+135
* clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definitionJerome Brunet2018-07-091-1/+0Star
* clk: meson-axg: add clocks required by pcie driverYixun Lan2018-07-092-1/+150
* clk: meson: remove unused clk-audio-divider driverJerome Brunet2018-07-093-119/+1Star
* clk: meson: stop rate propagation for audio clocksJerome Brunet2018-07-091-9/+7Star
* clk: meson: axg: add the audio clock controller driverJerome Brunet2018-07-094-0/+982
* clk: meson: add axg audio sclk divider driverJerome Brunet2018-07-093-1/+252
* clk: meson: add triple phase clock driverJerome Brunet2018-07-094-0/+94
* clk: meson: add clk-phase clock driverJerome Brunet2018-07-093-0/+72
* clk: meson: clean-up meson clock configurationJerome Brunet2018-07-091-9/+5Star
* clk: meson: remove obsolete register accessJerome Brunet2018-07-092-69/+4Star
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