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path: root/drivers/clk/qcom/clk-pll.c
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* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282Thomas Gleixner2019-06-051-9/+1Star
* clk: qcom: Enable FSM mode for votable alpha PLLsRajendra Nayak2016-11-021-28/+3Star
* clk: qcom: Convert to clk_hw based provider APIsStephen Boyd2015-08-251-6/+2Star
* Merge branch 'clk-determine-rate-struct' into clk-nextStephen Boyd2015-07-281-7/+11
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| * clk: change clk_ops' ->determine_rate() prototypeBoris Brezillon2015-07-281-7/+11
* | clk: qcom: Add support for SR2 PLLsGeorgi Djakov2015-07-081-0/+75
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* clk: qcom: fix simple_return.cocci warningsFengguang Wu2015-03-271-5/+1Star
* clk: Add rate constraints to clocksTomeu Vizoso2015-02-021-0/+1
* clk: Change clk_ops->determine_rate to return a clk_hw as the best parentTomeu Vizoso2014-12-041-1/+1
* clk: qcom: Add support for setting rates on PLLsStephen Boyd2014-09-231-1/+67
* clk: qcom: pll: Add support for configuring SR PLLsStephen Boyd2014-07-161-3/+12
* clk: qcom: Add support for phase locked loops (PLLs)Stephen Boyd2014-01-161-0/+222