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path: root/drivers/clk/qcom/gcc-msm8960.c
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* clk: qcom: Add MSM8960/APQ8064's HFPLLsStephen Boyd2018-10-171-0/+172
| | | | | | | | | | Describe the HFPLLs present on MSM8960 and APQ8064 devices. Acked-by: Rob Herring <robh@kernel.org> (bindings) Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Craig Tatlor <ctatlor97@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: drop CLK_SET_RATE_GATE from sdc clocksJerome Brunet2018-06-191-5/+0Star
| | | | | | | | | | | | | | | | | | the mmci driver (drivers/mmc/host/mmci.c) does the following sequence: * clk_prepare_enable() * clk_set_rate() on SDCx_clk which is a children of SDCx_src. SDCx_src has CLK_SET_RATE_GATE so this sequence should not be allowed but this was not enforced. IOW, the flag is ignored. Dropping the flag won't change anything to the current behaviour of the platform. CLK_SET_RATE_GATE is being fixed and enforced now. If the flag was kept, the mmci driver would receive -EBUSY when calling clk_set_rate() Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20180619134051.16726-2-jbrunet@baylibre.com
* clk: qcom: Remove CLK_IS_ROOTStephen Boyd2016-03-041-42/+0Star
| | | | | | This flag is a no-op now. Remove usage of the flag. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: msm8960: Fix ce3_src register offsetStephen Boyd2016-03-021-1/+1
| | | | | | | | | | The offset seems to have been copied from the sata clk. Fix it so that enabling the crypto engine source clk works. Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: msm8960: fix ce3_core clk enable registerSrinivas Kandagatla2016-02-221-1/+1
| | | | | | | | | This patch corrects the enable register offset which is actually 0x36cc instead of 0x36c4 Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Revert "clk: qcom: Specify LE device endianness"Stephen Boyd2016-02-121-2/+0Star
| | | | | | | | | | | | | | | | | This reverts commit 329cabcecf94d8d7821e729dda284ba9dec44c87. The commit that caused us to specify LE device endianness here, 29bb45f25ff3 (regmap-mmio: Use native endianness for read/write, 2015-10-29), has been reverted in mainline so now when we specify LE it actively breaks big endian kernels because the byte swapping in regmap-mmio is incorrect. Let's revert this change because it will 1) fix the big endian kernels and 2) be redundant to specify LE because that will become the default soon. Cc: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@baylibre.com> Cc: Mark Brown <broonie@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: Specify LE device endiannessStephen Boyd2015-11-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | All these clock controllers are little endian devices, but so far we've been relying on the regmap mmio bus handling this for us without explicitly stating that fact. After commit 4a98da2164cf (regmap-mmio: Use native endianness for read/write, 2015-10-29), the regmap mmio bus will read/write with the __raw_*() IO accessors, instead of using the readl/writel() APIs that do proper byte swapping for little endian devices. So if we're running on a big endian processor and haven't specified the endianness explicitly in the regmap config or in DT, we're going to switch from doing little endian byte swapping to big endian accesses without byte swapping, leading to some confusing results. On my apq8074 dragonboard, this causes the device to fail to boot as we access the clock controller with big endian IO accesses even though the device is little endian. Specify the endianness explicitly so that the regmap core properly byte swaps the accesses for us. Reported-by: Kevin Hilman <khilman@linaro.org> Tested-by: Tyler Baker <tyler.baker@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Cc: Simon Arlott <simon@fire.lp0.eu> Cc: Mark Brown <broonie@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: Move cxo/pxo/xo into dt filesStephen Boyd2015-11-161-8/+6Star
| | | | | | | | | | | | | Put these clocks into the dt files instead of registering them from C code. This provides a few benefits. It allows us to specify the frequency of these clocks at the board level instead of hard-coding them in the driver. It allows us to insert an RPM clock in between the consumers of the crystals and the actual clock. And finally, it helps us transition the GCC driver to use RPM clocks when that configuration is enabled. Cc: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: create virtual child device for TSENSRajendra Nayak2015-10-091-1/+18
| | | | | | | | | | | | | | 8960 family of devices have TSENS as part of GCC in hardware. Hence DT would represent a GCC node with GCC properties as well as TSENS. Create a virtual platform child device here for TSENS so the driver can probe it and use the parent (GCC) to extract DT properties. Suggested-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> [sboyd@codeaurora.org: Massaged to work with devm friendly qcom_cc_probe()] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: Drop calls to qcom_cc_remove()Stephen Boyd2015-10-091-1/+0Star
| | | | | | | | Now that qcom_cc_remove() is a nop, drop calls to qcom_cc_remove() and any empty driver remove functions. Cc: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: Constify the parent names arraysGeorgi Djakov2015-07-071-6/+6
| | | | | | | | Make const both the array and the strings, so they can be moved to .rodata section. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: Introduce parent_map tablesGeorgi Djakov2015-03-241-15/+17
| | | | | | | | | | | | | | | | | | | | | In the current parent mapping code, we can get duplicate or inconsistent indexes, which leads to discrepancy between the number of elements in the array and the number of parents. Until now, this was solved with some reordering but this is not always possible. This patch introduces index tables that are used to define the relations between the PLL source and the hardware mux configuration value. To accomplish this, here we do the following: - Define a parent_map struct to map the relations between PLL source index and register configuration value. - Add a qcom_find_src_index() function for finding the index of a clock matching the specific PLL configuration. - Update the {set,get}_parent RCG functions use the newly introduced parent_map struct. - Convert all existing drivers to the new parent_map tables. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: Add PLL4 vote clockStephen Boyd2015-02-251-0/+13
| | | | | | | This clock is needed for most audio clock frequencies. Add it. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: qcom: drop owner assignment from platform_driversWolfram Sang2014-10-201-1/+0Star
| | | | | | | A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* clk: qcom: Fully support apq8064 global clock controlStephen Boyd2014-07-111-4/+569
| | | | | | | Add in the handful of new clocks and introduce a new reset table with the few new resets. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: add clocks necessary for apq8064 sdccSrinivas Kandagatla2014-07-111-0/+12
| | | | | | | | | This patch adds clocks necessary for SD card controller on apq8064 SOC. Without this patch the clocks are not visible to the sdcc driver. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: Various fixes for MSM8960's global clock controllerKumar Gala2014-04-301-2/+2
| | | | | | | | | | | | | | | * Remove CE2_SLEEP_CLK, doesn't exist on 8960 family SoCs * Fix incorrect offset for PMIC_SSBI2_RESET * Fix typo: SIC_TIC -> SPS_TIC_H SFAB_ADM0_M2_A_CLK -> SFAB_ADM0_M2_H_CLK * Fix naming convention: SFAB_CFPB_S_HCLK -> SFAB_CFPB_S_H_CLK SATA_SRC_CLK -> SATA_CLK_SRC Signed-off-by: Kumar Gala <galak@codeaurora.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: qcom: Add basic support for APQ8064 global clock controller clocksKumar Gala2014-04-301-3/+27
| | | | | | | | | | | | | | The APQ8064 and MSM8960 share a significant amount of clock data and code between the two SoCs. Rather than duplicating the data we just add support for a unqiue APQ8064 clock table into the MSM8960 code. For now add just enough clocks to get a basic serial port going on an APQ8064 device. Signed-off-by: Kumar Gala <galak@codeaurora.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: trivial conflict due to missing ipq8064 support]
* clk: qcom: Consolidate common probe codeStephen Boyd2014-04-301-65/+12Star
| | | | | | | | | | Most of the probe code is the same between all the different clock controllers. Consolidate the code into a common.c file. This makes changes to the common probe parts easier and reduces chances for bugs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: qcom: Add support for MSM8960's global clock controller (GCC)Stephen Boyd2014-01-161-0/+2993
Add a driver for the global clock controller found on MSM8960 based platforms. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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