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path: root/drivers/clk/rockchip/clk-rk3228.c
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-07-171-1/+2
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| * clk: rockchip: export HDMIPHY clock on rk3228Heiko Stuebner2019-06-271-1/+1
| * clk: rockchip: add 1.464GHz cpu-clock rate to rk3228Justin Swartz2019-05-201-0/+1
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner2019-05-301-10/+1Star
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* clk: Remove io.h from clk-provider.hStephen Boyd2019-05-151-0/+1
* clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228Shawn Lin2018-03-231-1/+1
* clk: rockchip: add rk3228 SCLK_SDIO_SRC clk idElaine Zhang2017-08-221-1/+1
* clk: rockchip: mark noc and some special clk as critical on rk3228Elaine Zhang2017-06-021-1/+29
* clk: rockchip: export more rk3228 clocks idsElaine Zhang2017-06-021-46/+46
* clk: rockchip: fix up the RK3228 clk cpu setting tableElaine Zhang2017-05-171-12/+30
* clk: rockchip: export rk3228 MAC clocksXing Zheng2016-07-011-11/+11
* clk: rockchip: rename rk3228 sclk_macphy_50m to sclk_mac_extclkXing Zheng2016-07-011-3/+3
* clk: rockchip: export rk3228 audio clocksXing Zheng2016-07-011-4/+4
* clk: rockchip: include rk3228 downstream muxes into fractional dividersXing Zheng2016-07-011-29/+52
* clk: rockchip: fix incorrect rk3228 clock registersXing Zheng2016-06-221-9/+9
* clk: rockchip: release io resource when failing to init clkShawn Lin2016-03-271-0/+1
* clk: rockchip: Add support for multiple clock providersXing Zheng2016-03-271-5/+12
* clk: rockchip: allow varying mux parameters for cpuclk pll-sourcesXing Zheng2016-03-271-0/+3
* clk: rockchip: set the clock ids for RK3228 HDMIYakir Yang2016-02-261-4/+4
* clk: rockchip: set the clock ids for RK3228 VOPYakir Yang2016-02-261-3/+3
* clk: rockchip: add the tsadc clocks found on rk3228 SoCsCaesar Wang2016-02-261-2/+2
* clk: rockchip: convert manually created factor clocks to the new typeHeiko Stuebner2016-02-041-27/+5Star
* clk: rockchip: fix wrong mmc phase shift for rk3228Shawn Lin2016-01-281-3/+3
* clk: rockchip: only enter pll slow-mode directly before reboots on rk3288Heiko Stuebner2015-12-211-1/+1
* clk: rockchip: add clock controller for rk3228Jeffy Chen2015-12-121-0/+678