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path: root/drivers/clk/samsung/clk-exynos5420.c
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* clk: samsung: exynos542x: Move MSCL subsystem clocks to its sub-CMUMarek Szyprowski2019-08-081-14/+34
| | | | | | | | | | | | | | | | | | M2M scaler clocks require special handling of their parent bus clock during power domain on/off sequences. MSCL clocks were not initially added to the sub-CMU handler, because that time there was no driver for the M2M scaler device and it was not possible to test it. This patch fixes this issue. Parent clock for M2M scaler devices is now properly preserved during MSC power domain on/off sequence. This gives M2M scaler devices proper performance: fullHD XRGB32 image 1000 rotations test takes 3.17s instead of 45.08s. Fixes: b06a532bf1fa ("clk: samsung: Add Exynos5 sub-CMU clock driver") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lkml.kernel.org/r/20190808121839.23892-1-m.szyprowski@samsung.com Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: samsung: exynos5800: Move MAU subsystem clocks to MAU sub-CMUSylwester Nawrocki2019-08-081-11/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes broken sound on Exynos5422/5800 platforms after system/suspend resume cycle in cases where the audio root clock is derived from MAU_EPLL_CLK. In order to preserve state of the USER_MUX_MAU_EPLL_CLK clock mux during system suspend/resume cycle for Exynos5800 we group the MAU block input clocks in "MAU" sub-CMU and add the clock mux control bit to .suspend_regs. This ensures that user configuration of the mux is not lost after the PMU block changes the mux setting to OSC_DIV when switching off the MAU power domain. Adding the SRC_TOP9 register to exynos5800_clk_regs[] array is not sufficient as at the time of the syscore_ops suspend call MAU power domain is already turned off and we already save and subsequently restore an incorrect register's value. Fixes: b06a532bf1fa ("clk: samsung: Add Exynos5 sub-CMU clock driver") Reported-by: Jaafar Ali <jaafarkhalaf@gmail.com> Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Jaafar Ali <jaafarkhalaf@gmail.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lkml.kernel.org/r/20190808144929.18685-2-s.nawrocki@samsung.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: samsung: Change signature of exynos5_subcmus_init() functionSylwester Nawrocki2019-08-081-26/+34
| | | | | | | | | | | | | In order to make it easier in subsequent patch to create different subcmu lists for exynos5420 and exynos5800 SoCs the code is rewritten so we pass an array of pointers to the subcmus initialization function. Fixes: b06a532bf1fa ("clk: samsung: Add Exynos5 sub-CMU clock driver") Tested-by: Jaafar Ali <jaafarkhalaf@gmail.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lkml.kernel.org/r/20190808144929.18685-1-s.nawrocki@samsung.com Reviewed-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2019-07-171-7/+71
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This round of clk driver and framework updates is heavy on the driver update side. The two main highlights in the core framework are the addition of an bulk clk_get API that handles optional clks and an extra debugfs file that tells the developer about the current parent of a clk. The driver updates are dominated by i.MX in the diffstat, but that is mostly because that SoC has started converting to the clk_hw style of clk registration. The next big update is in the Amlogic meson clk driver that gained some support for audio, cpu, and temperature clks while fixing some PLL issues. Finally, the biggest thing that stands out is the conversion of a large part of the Allwinner sunxi-ng driver to the new clk parent scheme that uses less strings and more pointer comparisons to match clk parents and children up. In general, it looks like we have a lot of little fixes and tweaks here and there to clk data along with the normal addition of a handful of new drivers and a couple new core framework features. Core: - Add a 'clk_parent' file in clk debugfs - Add a clk_bulk_get_optional() API (with devm too) New Drivers: - Support gated clk controller on MIPS based BCM63XX SoCs - Support SiLabs Si5341 and Si5340 chips - Support for CPU clks on Raspberry Pi devices - Audsys clock driver for MediaTek MT8516 SoCs Updates: - Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme - Small frequency support for SiLabs Si544 chips - Slow clk support for AT91 SAM9X60 SoCs - Remove dead code in various clk drivers (-Wunused) - Support for Marvell 98DX1135 SoCs - Get duty cycle of generic pwm clks - Improvement in mmc phase calculation and cleanup of some rate defintions - Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs - Add GPIO, SNVS and GIC clocks for i.MX8 drivers - Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock - Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting - Add clks for new Exynos5422 Dynamic Memory Controller driver - Clock definition for Exynos4412 Mali - Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3 - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M - Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs - TI clock probing done from DT by default instead of firmware - Fix Amlogic Meson mpll fractional part and spread sprectrum issues - Add Amlogic meson8 audio clocks - Add Amlogic g12a temperature sensors clocks - Add Amlogic g12a and g12b cpu clocks - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N - Add CMM (Color Management Module) clocks on Renesas R-Car M3-W - Add Clock Domain support on Renesas RZ/N1" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (190 commits) clk: consoldiate the __clk_get_hw() declarations clk: sprd: Add check for return value of sprd_clk_regmap_init() clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK clk: Add Si5341/Si5340 driver dt-bindings: clock: Add silabs,si5341 clk: clk-si544: Implement small frequency change support clk: add BCM63XX gated clock controller driver devicetree: document the BCM63XX gated clock bindings clk: at91: sckc: use dedicated functions to unregister clock clk: at91: sckc: improve error path for sama5d4 sck registration clk: at91: sckc: remove unnecessary line clk: at91: sckc: improve error path for sam9x5 sck register clk: at91: sckc: add support to free slow clock osclillator clk: at91: sckc: add support to free slow rc oscillator clk: at91: sckc: add support to free slow oscillator clk: rockchip: export HDMIPHY clock on rk3228 clk: rockchip: add watchdog pclk on rk3328 clk: rockchip: add clock id for hdmi_phy special clock on rk3228 clk: rockchip: add clock id for watchdog pclk on rk3328 clk: at91: sckc: add support for SAM9X60 ...
| * clk: samsung: add new clocks for DMC for Exynos5422 SoCLukasz Luba2019-06-061-6/+55
| | | | | | | | | | | | | | | | | | | | | | This patch provides support for clocks needed for Dynamic Memory Controller in Exynos5422 SoC. It adds CDREX base register addresses, new DIV, MUX and GATE entries. Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: add BPLL rate table for Exynos 5422 SoCLukasz Luba2019-06-061-1/+16
| | | | | | | | | | | | | | | | | | | | Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory Controller frequencies for driver's DRAM timings. Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner2019-06-191-4/+1Star
|/ | | | | | | | | | | | | | | | | | | | | | | | | | Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* clk: samsung: exynos5420: Enable PERIS clocks for suspendMarek Szyprowski2018-10-051-0/+1
| | | | | | | | | | Ensure that clocks for core SoC modules (including TZPC0..9 modules) are enabled for suspend/resume cycle. This fixes suspend/resume support on Exynos5422-based Odroid XU3/XU4 boards. Suggested-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
* clk: samsung: exynos5420: Define CLK_SECKEY gate clock only or Exynos5420Joonyoung Shim2018-10-051-2/+1Star
| | | | | | | | | | | The bit of GATE_BUS_PERIS1 for CLK_SECKEY is just reserved on exynos5422/5800, not exynos5420. Define gate clk for exynos5420 to handle the bit only on exynos5420. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> [m.szyprow: rewrote commit subject] Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
* clk: samsung: exynos5420: Use generic helper for handling suspend/resumeMarek Szyprowski2018-10-051-66/+6Star
| | | | | | | | | Replace common suspend/resume handling code by generic helper. Almost no functional change, the only difference is in handling of hypothetical memory allocation failure on boot. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
* clk: samsung: exynos5420: Add more entries to EPLL rate tableSylwester Nawrocki2018-03-121-0/+3
| | | | | | | | | | Adding these EPLL output frequency entries allows to support all required audio sample rates on the CODEC and the HDMI interface on Peach-Pit Chromebook. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clkSylwester Nawrocki2018-03-121-1/+2
| | | | | | | | | | This allows changing the EPLL output frequency through the audio subsystem clock tree leaf clocks. This change is needed to support audio on the HDMI interface on Peach-Pi(t) Chromebook. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5420: Move PD-dependent clocks to Exynos5 sub-CMUMarek Szyprowski2018-03-061-26/+95
| | | | | | | | | | | | | | Clocks related to DISP, GSC and MFC blocks require special handling for power domain turn on/off sequences. Till now this was handled by Exynos power domain driver, but that approach was limited only to some special cases. This patch moves handling of those operations to clock controller driver. This gives more flexibility and allows fine tune values of some clock-specific registers. This patch moves handling of those mentioned clocks to Exynos5 sub-CMU driver instantiated from Exynos5420 driver. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: Add compile time PLL rate validatorsAndrzej Hajda2018-02-231-31/+31
| | | | | | | | | | | | | | | | | | | | Rates declared in PLL rate tables should match exactly rates calculated from PLL coefficients. To avoid possible mistakes we can use compile time validation. The patch introduces such validators and expands all initializers with additional input frequency parameter, required to validate rates. Since S3C24xx PLLs requires different validators two new macros have been introduced to deal with it. Also, since PLLs 4502 and 4508 have different formulas PLL_45XX_RATE has been replaced with PLL_4508_RATE. As the patch adds only compile time validators it should not have impact on compiled code. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: Drop useless alias in Exynos5420 clk driverMarek Szyprowski2017-10-091-2/+1Star
| | | | | | | | | Drop clkdev alias for "mout_aclk400_mscl" clock. It was not used at all and it was probably committed by accident. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: Fix m2m scaler clock on Exynos542xAndrzej Pietrasiewicz2017-09-291-1/+1
| | | | | | | | | | | | The TOP "aclk400_mscl" clock should be kept enabled all the time to allow proper access to power management control for MSC power domain and devices that are a part of it. This change is required for the scaler to work properly after domain power on/off sequence. Fixes: 318fa46cc60d ("clk/samsung: exynos542x: mark some clocks as critical") Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* Merge tag 'clk-v4.14-samsung' of ↵Stephen Boyd2017-08-241-8/+15
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next Pull Samsung clk driver updates from Sylwester Nawrocki: Changes in definitions of audio related clocks for Exynos5420/5422/5800 SoCs: a fix of mau_epll clock definition and changes enabling clock rate setting propagation on a path from the I2S IP block up the EPLL. * tag 'clk-v4.14-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: clk: samsung: exynos542x: Enable clock rate propagation up to the EPLL clk: samsung: Add CLK_SET_RATE_PARENT to some AUDSS CLK CON clocks clk: samsung: Fix mau_epll clock definition for exynos5422
| * clk: samsung: exynos542x: Enable clock rate propagation up to the EPLLSylwester Nawrocki2017-08-101-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | The CLK_SET_RATE_PARENT flag is added to clocks between the EPLL and the audio subsystem clock controller so that the EPLL's output frequency can be set indirectly with clk_set_rate() on a leaf clock. That should be safe as EPLL is normally only used to generate clock for the audio subsystem. With this change we can avoid passing the EPLL clock to the ASoC machine driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: Fix mau_epll clock definition for exynos5422Sylwester Nawrocki2017-08-091-3/+9
| | | | | | | | | | | | | | | | Parent clock of the MAU_EPLL gate clock on exynos5422 is "mout_user_mau_epll", not "mout_mau_epll_clk". This change only affects exynos5422/5800. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* | clk: samsung: exynos5420: The EPLL rate table correctionsSylwester Nawrocki2017-07-311-8/+8
|/ | | | | | | | | | | | | | | | | | | | | | This patch fixes values of the EPLL K coefficient and changes the EPLL output frequency values to match exactly what is possible to achieve with given M, P, S, K coefficients. This allows to avoid rounding errors and unexpected frequency being set with clk_set_rate(), due to recalc_rate returning different values than the PLL rate specified in the exynos5420_epll_24mhz_tbl table. E.g. this prevents a case where two consecutive clk_set_rate() calls with same argument result in different PLL output frequency. The PLL output frequencies have been calculated with formula: f = fxtal * (M * 2^16 + K) / (P * 2^S) / 2^16 where fxtal = 24000000. Fixes: 9842452acd ("clk: samsung: exynos542x: Add EPLL rate table") Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: samsung: exynos542x: Add EPLL rate tableSylwester Nawrocki2017-06-091-2/+17
| | | | | | | | | A specific clock rate table is added for EPLL so it is possible to set frequency of the EPLL output clock as multiple of various audio sampling rates. Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: Add missing exynos5420 audio related clocksSylwester Nawrocki2017-06-091-3/+7
| | | | | | | | | | This patch adds missing definitions of mux clocks required for using EPLL as the audio subsystem root clock on exynos5420/exynos5422 SoCs. Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk/samsung: exynos542x: mark some clocks as criticalMarek Szyprowski2017-01-101-7/+7
| | | | | | | | | | | | | | | | Some parent clocks of the Exynos542x clock blocks, which have separate power domains (like DISP, MFC, MSC, GSC, FSYS and G2D) must be always enabled to access any register related to power management unit or devices connected to it. For the time being, until a proper solution based on runtime PM is applied, mark those clocks as critical (instead of ignore unused or even no flags) to prevent disabling them. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> [Exynos5800 Peach Pi Chromebook] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: samsung: exynos5420: Add clocks for CMU_CDREX domainChanwoo Choi2016-09-091-0/+37
| | | | | | | | | | | This patch adds the mux/divider clocks for CMU_CDREX (DRAM Express Controller) which generates the clocks for DRAM and NoC (Network on Chip) bus. There is differnet source of MUX_MX_MSPLL_CCORE between exynos5420 and exynos5422, so each MUX_MX_MSPLL_CCORE uses the different parent source group. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5420: Set ID for aclk333 gate clockJavier Martinez Canillas2016-06-021-1/+1
| | | | | | | | | | | The aclk333 clock needs to be ungated during the MFC power domain switch, so set the clock ID to allow the Exynos power domain logic to lookup this clock if is defined in the MFC PD device tree node. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5420: Move sleep init function and PLL data to init sectionKrzysztof Kozlowski2016-06-021-3/+3
| | | | | | | | | The exynos5420_clk_sleep_init() function and arrays with initialization data of PLLs can be moved to init section because they are referenced only from other init-level symbols. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5420: Constify all clock initializersKrzysztof Kozlowski2016-06-021-15/+15
| | | | | | | All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: Remove useless check for return value of samsung_clk_initKrzysztof Kozlowski2016-06-021-2/+0Star
| | | | | | | | | The samsung_clk_init() cannot return NULL. Either it returns allocated memory or it panics. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos542x: Add the clock id for ACLKChanwoo Choi2016-04-151-30/+47
| | | | | | | | | | | | This patch adds the clock id for ACLK clock which is source clock of AMBA AXI bus. This clock should be handled in the bus frequency scaling driver. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Markus Reichl <m.reichl@fivetechno.de> Tested-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: Remove CLK_IS_ROOTStephen Boyd2016-03-031-6/+6
| | | | | | | This flag is a no-op now. Remove usage of the flag. Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: samsung: exynos542x: fix MFC clock hierarchy parentMarek Szyprowski2015-12-161-1/+1
| | | | | | | | Proper source for MFC block is mout_user_aclk333 (in datasheet named USER_MUX_ACLK_333), not the output of CLKDIV_ACLK_333 MUX. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos542x/5800: fix cpu clock configuration dataBartlomiej Zolnierkiewicz2015-12-161-3/+33
| | | | | | | | | | | | Fix cpu clock configuration data for Exynos5422/5800 SoCs (they use higher PCLK_DBG divider values than Exynos5420 and support additional frequencies). Based on Hardkernel's kernel for ODROID-XU3 board. Cc: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5420: add cpu clock configuration data and instantiate ↵Thomas Abraham2015-12-161-2/+56
| | | | | | | | | | | | | | | | cpu clock With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos5420. Changes by Bartlomiej: - split Exynos5420 support from the original patches - moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos542x: add missing parent GSCL block clocksMarek Szyprowski2015-12-161-4/+4
| | | | | | | | This patch adds clocks, which are required for preserving parent clock configuration on GSCL power domain on/off. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: Properly include clk.h and clkdev.hStephen Boyd2015-07-201-2/+1Star
| | | | | | | | | | | | | | Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Only include clk.h in files that are using it. The clkdev.h header isn't always used either, so remove it and add in slab.h where files were relying on it to include slab for them. Cc: Chanwoo Choi <cw00.choi@samsung.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge branch 'clk-fixes' into clk-nextMichael Turquette2015-05-081-0/+1
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| * clk: exynos5420: Restore GATE_BUS_TOP on suspendJavier Martinez Canillas2015-05-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ae43b3289186 ("ARM: 8202/1: dmaengine: pl330: Add runtime Power Management support v12") added pm support for the pl330 dma driver but it makes the clock for the Exynos5420 MDMA0 DMA controller to be gated during suspend and this in turn makes its parent clock aclk266_g2d to be gated. But the clock needs to be ungated prior suspend to allow the system to be suspend and resumed correctly. Add GATE_BUS_TOP register to the list of registers to be restored when the system enters into a suspend state so aclk266_g2d will be ungated. Thanks to Abhilash Kesavan for figuring out that this was the issue. Fixes: ae43b32 ("ARM: 8202/1: dmaengine: pl330: Add runtime Power Management support v12") Cc: stable@vger.kernel.org # 3.19+ Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Tested-by: Kevin Hilman <khilman@linaro.org> Tested-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* | clk: exynos: Staticize file-scope declarationsKrzysztof Kozlowski2015-05-061-5/+5
|/ | | | | | | Add missing static to local (file-scope only) symbols. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: exynos5420: Add IDs for clocks used in DISP1 power domainJavier Martinez Canillas2015-01-291-11/+12
| | | | | | | | | | | | | | | | | | | | | | | When a power domain is powered off on Exynos5420 SoC, the input clocks of the devices attached to this power domain are re-parented to oscclk and restored to the original parent after powering on the power domain. So a reference to the input and parent clocks for the devices attached to a power domain are needed to be able to do the re-parenting. The DISP1 pd includes modules which uses the following clocks: ACLK_200_DISP1 (MIXER and HDMILINK) ACLK_300_DISP1 (FIMD1) ACLK_400_DISP1 (Internal Buses) Each of these clocks are generated as the output of a clock mux so add an ID for all of these clock muxes and their parents to be referenced in the DISP1 power domain device node. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene@kernel.org>
* Merge tag 'clk-for-linus-3.17' of ↵Linus Torvalds2014-08-041-1/+60
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clock framework updates from Mike Turquette: "The clock framework changes for 3.17 are mostly additions of new clock drivers and fixes/enhancements to existing clock drivers. There are also some non-critical fixes and improvements to the framework core. Changes to the clock framework core include: - improvements to printks on errors - flattening the previously hierarchal structure of per-clock entries in debugfs - allow per-clock debugfs entries that are specific to a particular clock driver - configure initial clock parent and/or initial clock rate from Device Tree - several feature enhancements to the composite clock type - misc fixes New clock drivers added include: - TI Palmas PMIC - Allwinner A23 SoC - Qualcomm APQ8084 and IPQ8064 SoCs - Rockchip rk3188, rk3066 and rk3288 SoCs - STMicroelectronics STiH407 SoC - Cirrus Logic CLPS711X SoC Many fixes, feature enhancements and further clock tree support for existing clock drivers also were merged, such as Samsung's "ARMCLK down" power saving feature for their Exynos4 & Exynos5 SoCs" * tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux: (86 commits) clk: Add missing of_clk_set_defaults export clk: checking wrong variable in __set_clk_parents() clk: Propagate any error return from debug_init() clk: clps711x: Add DT bindings documentation clk: Add CLPS711X clk driver clk: st: Use round to closest divider flag clk: st: Update frequency tables for fs660c32 and fs432c65 clk: st: STiH407: Support for clockgenA9 clk: st: STiH407: Support for clockgenD0/D2/D3 clk: st: STiH407: Support for clockgenC0 clk: st: Add quadfs reset handling clk: st: Add polarity bit indication clk: st: STiH407: Support for clockgenA0 clk: st: STiH407: Support for A9 MUX Clocks clk: st: STiH407: Support for Flexgen Clocks clk: st: Adds Flexgen clock binding clk: st: Remove uncessary (void *) cast clk: st: use static const for clkgen_pll_data tables clk: st: use static const for stm_fs tables clk: st: Update ST clock binding documentation ...
| * clk: samsung: register exynos5420 apll/kpll configuration dataThomas Abraham2014-07-261-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | Register the PLL configuration data for APLL and KPLL on Exynos5420. This configuration data table specifies PLL coefficients for supported PLL clock speeds when a 24MHz clock is supplied as the input clock source for these PLLs. Cc: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Amit Daniel Kachhap <amit.daniel@samsung.com> Tested-by: Arjun K.V <arjun.kv@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: exynos5420: Setup clocks before system suspendVikas Sajjan2014-07-261-0/+29
| | | | | | | | | | | | | | | | | | | | | | Prior to suspending the system, we need to ensure that certain clock source and gate registers are unmasked. while at it, add these clks to save/restore list also. Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: Make of_device_id array constKrzysztof Kozlowski2014-07-261-1/+1
| | | | | | | | | | | | | | | | | | Array of struct of_device_id may be be const as expected by of_match_table field and of_find_matching_node_and_match() function. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| * clk: samsung: Register clk provider only after registering its all clocksSylwester Nawrocki2014-06-301-0/+2
| | | | | | | | | | | | | | | | | | | | Ensure the clock provider is not registered until after all its related clocks were created and are ready to use. Currently there are races possible and any (of_)clk_get() call right after a clock provider's clk_init_cb callback call may fail. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* | Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds2014-07-131-30/+55
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clock driver fixes from Mike Turquette: "This batch of fixes is for a handful of clock drivers from Allwinner, Samsung, ST & TI. Most of them are of the "this hardware won't work without this fix" variety, including patches that fix platforms that did not boot under certain configurations. Other fixes are the result of changes to the clock core introduced in 3.15 that had subtle impacts on the clock drivers. There are no fixes to the clock framework core in this pull request" * tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux: clk: spear3xx: Set proper clock parent of uart1/2 clk: spear3xx: Use proper control register offset clk: qcom: HDMI source sel is 3 not 2 clk: sunxi: fix devm_ioremap_resource error detection code clk: s2mps11: Fix double free corruption during driver unbind clk: ti: am43x: Fix boot with CONFIG_SOC_AM33XX disabled clk: exynos5420: Remove aclk66_peric from the clock tree description clk/exynos5250: fix bit number for tv sysmmu clock clk: s3c64xx: Hookup SPI clocks correctly clk: samsung: exynos4: Remove SRC_MASK_ISP gates clk: samsung: add more aliases for s3c24xx clk: samsung: fix several typos to fix boot on s3c2410 clk: ti: set CLK_SET_RATE_NO_REPARENT for ti,mux-clock clk: ti: am43x: Fix boot with CONFIG_SOC_AM33XX disabled clk: ti: dra7: return error code in failure case clk: ti: apll: not allocating enough data
| * clk: exynos5420: Remove aclk66_peric from the clock tree descriptionDoug Anderson2014-06-301-30/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "aclk66_peric" clock is a gate clock with a whole bunch of gates underneath it. This big gate isn't very useful to include in our clock tree. If any of the children need to be turned on then the big gate will need to be on anyway. ...and there are plenty of other "big gates" that aren't described in our clock tree, some of which shut off collections of clocks that have no relationship in the hierarchy so are hard to model. "aclk66_peric" is causing earlyprintk problems since it gets disabled as part of the boot process, so let's just remove it. Strangely (and for no good reason) this clock is exported as part of the common clock bindings. Remove it since there are no in-kernel device trees using it and no reason anyone out of tree should refer to it either. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* | clk: exynos5420: Add IDs for clocks used in PD mfcArun Kumar K2014-07-111-2/+4
|/ | | | | | | | | | Adds IDs for MUX clocks to be used by power domain for MFC for doing re-parenting while pd on/off. Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* clk: exynos5420: Add 5800 specific clocksAlim Akhtar2014-05-191-56/+253
| | | | | | | | | | | | Exynos5800 clock structure is mostly similar to 5420 with only a small delta changes. So the 5420 clock file is re-used for 5800 also. The common clocks for both are seggreagated and few clocks which are different for both are separately initialized. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* clk: samsung: exynos5420: add more registers to restore listShaik Ameer Basha2014-05-141-0/+12
| | | | | | | | | This patch adds more register offsets to the list for preserving their values during S2R. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5420: add misc clocksShaik Ameer Basha2014-05-141-3/+11
| | | | | | | | | This patch adds some missing miscellaneous clocks specific to exynos5420. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
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