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path: root/drivers/clk/socfpga
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* clk: socfpga: stratix10: fix the sdmmc_free_clk muxDinh Nguyen2018-07-061-1/+1
* clk: socfpga: stratix10: fix the parents of mpu_free_clkDinh Nguyen2018-07-061-1/+6
* clk: socfpga: stratix10: suppress unbinding platform's clock driverDinh Nguyen2018-05-151-0/+1
* clk: socfpga: stratix10: use platform driver APIsDinh Nguyen2018-05-151-22/+17Star
* clk: socfpga: stratix10: add clock driver for Stratix10 platformDinh Nguyen2018-04-067-5/+853
* License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman2017-11-021-0/+1
* clk: socfpga: Fix the smplsel on Arria10 and Stratix10Dinh Nguyen2017-06-202-1/+4
* clk: socfpga: allow for multiple parents on Arria10 periph clocksDinh Nguyen2016-02-222-9/+4Star
* clk: socfpga: fix __init annotationArnd Bergmann2016-02-081-1/+1
* clk: socfpga: Add a second parent option for the dbg_base_clkDinh Nguyen2015-08-252-4/+15
* clk: socfpga: switch to GENMASK()Andy Shevchenko2015-07-285-5/+4Star
* clk: socfpga: Remove clk.h and clkdev.h includesStephen Boyd2015-07-207-7/+6Star
* clk: socfpga: remove a stray tabDan Carpenter2015-06-101-1/+1
* clk: socfpga: make use of of_clk_parent_fill helper functionDinh Nguyen2015-06-062-11/+2Star
* clk: socfpga: add a clock driver for the Arria 10 platformDinh Nguyen2015-05-226-1/+469
* clk: socfpga: update clk.h so for Arria10 platform to useDinh Nguyen2015-05-222-5/+5
* clk: socfpga: Silence sparse warningStephen Boyd2015-05-151-1/+1
* clk: socfpga: Silence sparse warningStephen Boyd2015-05-151-1/+1
* Merge tag 'socfpga-clk-update-for-v3.16' of git://git.rocketboards.org/linux-...Mike Turquette2014-05-133-4/+23
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| * clk: socfpga: add divider registers to the main pll outputsDinh Nguyen2014-05-123-4/+23
* | clk: socfpga: fix clock driver for 3.15Dinh Nguyen2014-04-302-20/+10Star
|/
* clk: socfpga: Fix section mismatch warningDinh Nguyen2014-03-191-1/+1
* clk: socfpga: Support multiple parents for the pll clocksDinh Nguyen2014-02-261-4/+22
* clk: socfpga: Fix integer overflow in clock calculationDinh Nguyen2014-02-261-3/+5
* clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk"Dinh Nguyen2014-02-181-0/+68
* clk: socfpga: split clk codeSteffen Trumtrar2014-02-186-306/+462
* clk: socfpga: fix define typoSteffen Trumtrar2014-02-181-3/+3
* clk: socfpga: remove unused fieldSteffen Trumtrar2014-02-181-1/+0Star
* clk: socfpga: Remove socfpga_init_clocksDinh Nguyen2014-02-181-10/+0Star
* clk: socfpga: Look for the GPIO_DB_CLK by its offsetDinh Nguyen2014-02-181-2/+3
* clk: socfpga: Map the clk manager base address in the clock driverDinh Nguyen2014-02-181-4/+16
* clk: socfpga: Use NULL instead of 0Sachin Kamat2013-12-201-1/+1
* clk: socfpga: Remove check for "reg" property in socfpga_clk_initDinh Nguyen2013-11-271-3/+1Star
* clk: socfpga: Fix incorrect sdmmc clock nameDinh Nguyen2013-10-081-1/+1
* ARM: socfpga: Add support to gate peripheral clocksDinh Nguyen2013-06-121-9/+185
* ARM: socfpga: Upgrade clk driver for socfpga to make use of dts clock entriesDinh Nguyen2013-04-151-21/+142
* ARM: socfpga: initial support for Altera's SOCFPGA platformDinh Nguyen2012-07-192-0/+52
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