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path: root/drivers/clk/sunxi-ng
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* clk: sunxi-ng: Provide a default reset hookMaxime Ripard2017-08-301-0/+12
* clk: sunxi-ng: a83t: Support new timing mode for mmc2 clockChen-Yu Tsai2017-08-301-8/+2Star
* clk: sunxi-ng: Add MP_MMC clocks that support MMC timing modes switchingChen-Yu Tsai2017-08-302-0/+110
* clk: sunxi-ng: Add interface to query or configure MMC timing modes.Chen-Yu Tsai2017-08-303-0/+75
* clk: sunxi-ng: sun5i: Add clk_set_rate_parent to the CPU clockMaxime Ripard2017-07-241-1/+1
* clk: sunxi-ng: Staticize ccu_mux_helper_unapply_prediv()Stephen Boyd2017-06-161-1/+1
* Merge tag 'sunxi-clk-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel...Stephen Boyd2017-06-1621-260/+1562
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| * clk: sunxi-ng: Move all clock types to a libraryStephen Boyd2017-06-072-132/+22Star
| * clk: sunxi-ng: a83t: Add support for A83T's PRCMChen-Yu Tsai2017-06-071-0/+107
| * clk: sunxi-ng: select SUNXI_CCU_MULT for sun8i-a83tArnd Bergmann2017-06-071-0/+1
| * clk: sunxi-ng: a83t: Fix audio PLL divider offsetChen-Yu Tsai2017-06-071-1/+1
| * clk: sunxi-ng: a83t: Fix PLL lock status register offsetChen-Yu Tsai2017-06-071-1/+1
| * clk: sunxi-ng: Add driver for A83T CCUChen-Yu Tsai2017-06-074-0/+998
| * clk: sunxi-ng: Support multiple variable pre-dividersChen-Yu Tsai2017-06-079-47/+54
| * clk: sunxi-ng: de2: fix wrong pointer passed to PTR_ERR()Wei Yongjun2017-06-071-1/+1
| * clk: sunxi-ng: sun5i: Export video PLLsMaxime Ripard2017-06-071-2/+4
| * clk: sunxi-ng: mux: Re-adjust parent rateMaxime Ripard2017-06-071-5/+28
| * clk: sunxi-ng: mux: Change pre-divider application function prototypeMaxime Ripard2017-06-075-33/+28Star
| * clk: sunxi-ng: mux: split out the pre-divider computation codeMaxime Ripard2017-06-071-12/+20
| * clk: sunxi-ng: mux: Don't just rely on the parent for CLK_SET_RATE_PARENTMaxime Ripard2017-06-071-13/+1Star
| * clk: sunxi-ng: div: Switch to divider_round_rateMaxime Ripard2017-06-071-23/+4Star
| * clk: sunxi-ng: Pass the parent and a pointer to the clocks round rateMaxime Ripard2017-06-076-18/+25
| * clk: sunxi-ng: explicitly include linux/spinlock.hTobias Klauser2017-06-071-0/+1
| * clk: sunxi-ng: add support for DE2 CCUIcenowy Zheng2017-06-074-0/+294
* | Merge tag 'sunxi-clk-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/...Stephen Boyd2017-06-155-4/+9
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| * clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCMChen-Yu Tsai2017-05-311-1/+3
| * clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCMChen-Yu Tsai2017-05-311-1/+3
| * clk: sunxi-ng: enable SUNXI_CCU_MP for PRCMArnd Bergmann2017-05-181-0/+1
| * clk: sunxi-ng: v3s: Fix usb otg device reset bitYong Deng2017-05-141-1/+1
| * clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offsetChen-Yu Tsai2017-05-141-1/+1
* | clk: sunxi-ng: sun5i: Fix ahb_bist_clk definitionBoris Brezillon2017-05-251-1/+1
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2017-05-1017-53/+710
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| * Merge tag 'sunxi-clk-for-4.12-2' of https://git.kernel.org/pub/scm/linux/kern...Stephen Boyd2017-04-227-18/+17Star
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| | * clk: sunxi-ng: a80: Fix audio PLL comment not matching actual codeChen-Yu Tsai2017-04-131-2/+1Star
| | * clk: sunxi-ng: Fix round_rate/set_rate multiplier minimum mismatchChen-Yu Tsai2017-04-132-3/+3
| | * clk: sunxi-ng: use 1 as fallback for minimum multiplierChen-Yu Tsai2017-04-134-11/+11
| | * clk: sunxi-ng: fix PRCM CCU CLK_NUMBER valueIcenowy Zheng2017-04-101-1/+1
| | * clk: sunxi-ng: fix PRCM CCU ir clk parentIcenowy Zheng2017-04-101-1/+1
| * | Merge tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel...Stephen Boyd2017-04-1913-37/+695
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| | * clk: sunxi-ng: Display index when clock registration failsPriit Laes2017-04-061-2/+2
| | * clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factorChen-Yu Tsai2017-04-051-7/+11
| | * clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocksChen-Yu Tsai2017-04-051-18/+52
| | * clk: sunxi-ng: mult: Support PLL lock detectionChen-Yu Tsai2017-04-052-0/+4
| | * clk: sunxi-ng: add support for PRCM CCUsIcenowy Zheng2017-04-044-0/+247
| | * clk: sunxi-ng: sun5i: Fix mux width for csi clockPriit Laes2017-03-061-1/+1
| | * clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCsPeter Robinson2017-03-061-0/+8
| | * clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driverIcenowy Zheng2017-03-063-9/+323
| | * clk: sunxi-ng: gate: Support common pre-dividersChen-Yu Tsai2017-03-061-0/+47
* | | clk: sunxi-ng: always select CCU_GATEArnd Bergmann2017-04-281-1/+1
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* | clk: sunxi-ng: a33: gate then ungate PLL CPU clk after rate changeChen-Yu Tsai2017-04-131-0/+11
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