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path: root/drivers/clk/tegra
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* Merge tag 'tegra-for-4.4-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Michael Turquette2015-10-207-113/+163
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| * clk: tegra: Modify tegra_audio_clk_init to accept more pllsRhyland Klein2015-10-205-11/+56
| * clk: tegra: Update struct tegra_clk_pll_params kerneldocThierry Reding2015-10-201-3/+15
| * clk: tegra: Fix comments for structure definitionsRhyland Klein2015-10-201-37/+37
| * clk: tegra: dfll: Monitor code is DEBUG_FS onlyThierry Reding2015-10-201-50/+49Star
| * clk: tegra: Unlock top rates for Tegra124 DFLL clockMikko Perttunen2015-09-152-14/+8Star
* | clk: tegra: delete unneeded of_node_putJulia Lawall2015-10-121-3/+1Star
* | clk: tegra: dfll: Properly protect OPP listThierry Reding2015-09-171-1/+7
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* clk: tegra: Fix some static checker problemsStephen Boyd2015-08-262-7/+9
* Merge tag 'tegra-for-4.3-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Stephen Boyd2015-08-2610-9/+2304
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| * clk: tegra: Add the DFLL as a possible parent of the cclk_g clockTuomas Tynkkynen2015-07-161-1/+3
| * clk: tegra: Save/restore CCLKG_BURST_POLICY on suspendTuomas Tynkkynen2015-07-161-0/+14
| * clk: tegra: Add Tegra124 DFLL clocksource platform driverTuomas Tynkkynen2015-07-164-4/+172
| * clk: tegra: Add DFLL DVCO reset control for Tegra124Paul Walmsley2015-07-161-0/+68
| * clk: tegra: Introduce ability for SoC-specific reset control callbacksMikko Perttunen2015-07-162-8/+34
| * clk: tegra: Add functions for parsing CVB tablesTuomas Tynkkynen2015-07-162-0/+207
| * clk: tegra: Add closed loop support for the DFLLTuomas Tynkkynen2015-07-161-3/+663
| * clk: tegra: Add library for the DFLL clock source (open-loop mode)Tuomas Tynkkynen2015-07-163-0/+1150
* | clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)Stephen Boyd2015-08-251-4/+4
* | clk: tegra: Convert to clk_hw based provider APIsStephen Boyd2015-08-252-10/+10
* | Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd2015-07-2816-16/+2Star
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| * | clk: tegra: Properly include clk.hStephen Boyd2015-07-2016-16/+2Star
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* / clk: change clk_ops' ->determine_rate() prototypeBoris Brezillon2015-07-281-13/+15
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* clk: tegra: Fix hda2codec_2x clock name for Tegra30Marcel Ziswiler2015-05-131-1/+1
* clk: tegra: EMC clock driver depends on EMC driverThierry Reding2015-05-133-1/+14
* clk: tegra: Have EMC clock implement determine_rate()Tomeu Vizoso2015-05-131-12/+23
* clk: tegra: Set the EMC clock as the parent of the MC clockTomeu Vizoso2015-05-131-12/+1Star
* clk: tegra: Add EMC clock driverMikko Perttunen2015-05-134-2/+535
* clk: tegra: Remove old Tegra124 EMC clockMikko Perttunen2015-05-131-1/+0Star
* clk: tegra: Use the proper parent for plld_dsiThierry Reding2015-04-101-6/+8
* clk: tegra: Use generic tegra_osc_clk_init() on Tegra114Thierry Reding2015-04-101-31/+3Star
* clk: tegra: Model oscillator as clockThierry Reding2015-04-104-17/+21
* clk: tegra: Add peripheral registers for bank YThierry Reding2015-04-101-0/+14
* clk: tegra: Register the proper number of resetsThierry Reding2015-04-101-1/+1
* clk: tegra: Remove needless initializationsThierry Reding2015-04-101-3/+3
* clk: tegra: Use consistent indentationThierry Reding2015-04-101-10/+10
* clk: tegra: Various whitespace cleanupsThierry Reding2015-04-102-1/+2
* clk: tegra: Enable HDA to HDMI clocks on Tegra124Dylan Reid2015-04-101-0/+5
* clk: tegra: Fix a bunch of sparse warningsThierry Reding2015-04-101-1/+1
* clk: tegra: Fix typo tabel -> tableThierry Reding2015-04-101-1/+1
* clk: Replace explicit clk assignment with __clk_hw_set_clkJavier Martinez Canillas2015-02-181-7/+7
* clk: tegra: Define PLLD_DSI and remove dsia(b)_muxMark Zhang2015-02-024-26/+24Star
* clk: tegra: Add support for the Tegra132 CAR IP blockPaul Walmsley2015-02-023-12/+129
* clk: tegra: make tegra_clocks_apply_init_table() arch_initcallPeter De Schrijver2015-02-021-2/+5
* clk: tegra: Fix order of arguments in WARNTomeu Vizoso2015-02-021-4/+4
* clk: tegra124: Add init data for dsi lp clocksSean Paul2015-02-021-0/+2
* clk: tegra: SDMMC controllers are on APBAndrew Bresticker2015-02-021-8/+8
* clk: tegra: Implement memory-controller clockThierry Reding2014-11-266-4/+40
* clk: tegra: Make clock initialization more robustTomeu Vizoso2014-09-181-2/+7
* clk: tegra124: Add PLL_M_UD and PLL_C_UD clocksMikko Perttunen2014-09-181-0/+8
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-01 02:45:23 +0200