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path:
root
/
drivers
/
clk
/
tegra
Commit message (
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Author
Age
Files
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clk: tegra: Add sdmmc mux divider clock
Peter De-Schrijver
2018-07-25
3
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+278
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clk: tegra: Refactor fractional divider calculation
Peter De Schrijver
2018-07-25
4
-25
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+52
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clk: tegra: Fix includes required by fence_udelay()
Aapo Vienamo
2018-07-25
1
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+1
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Merge branches 'clk-imx-critical', 'clk-tegra-bpmp', 'clk-tegra-124', 'clk-te...
Stephen Boyd
2018-08-15
4
-7
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+15
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clk: tegra: emc: Avoid out-of-bounds bug
Dmitry Osipenko
2018-07-09
1
-1
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+1
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clk: tegra: Mark Memory Controller clock as critical
Dmitry Osipenko
2018-07-09
1
-2
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+3
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clk: tegra: Make vde a child of pll_c3
Thierry Reding
2018-07-09
1
-1
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+1
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clk: tegra: Make vic03 a child of pll_c3
Thierry Reding
2018-07-09
1
-0
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+1
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clk: tegra: bpmp: Don't crash when a clock fails to register
Mikko Perttunen
2018-07-09
1
-3
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+9
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treewide: kzalloc() -> kcalloc()
Kees Cook
2018-06-13
1
-3
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+4
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Merge branches 'clk-imx7d', 'clk-hisi-stub', 'clk-mvebu', 'clk-imx6-epit' and...
Stephen Boyd
2018-06-04
1
-31
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+11
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clk: tegra: no need to check return value of debugfs_create functions
Greg Kroah-Hartman
2018-06-02
1
-31
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+11
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clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20
Dmitry Osipenko
2018-05-18
7
-8
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+39
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clk: tegra20: Correct parents of CDEV1/2 clocks
Dmitry Osipenko
2018-05-18
1
-4
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+2
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clk: tegra20: Add DEV1/DEV2 OSC dividers
Dmitry Osipenko
2018-05-18
1
-0
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+14
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clk: tegra: Fix pll_u rate configuration
Marcel Ziswiler
2018-03-12
1
-0
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+2
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clk: tegra: Specify VDE clock rate
Dmitry Osipenko
2018-03-12
4
-1
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+4
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clk: tegra20: Correct PLL_C_OUT1 setup
Dmitry Osipenko
2018-03-12
1
-3
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+3
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clk: tegra: Mark HCLK, SCLK and EMC as critical
Dmitry Osipenko
2018-03-12
8
-36
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+26
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clk: tegra: MBIST work around for Tegra210
Peter De Schrijver
2018-03-08
1
-2
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+342
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clk: tegra: add fence_delay for clock registers
Peter De Schrijver
2018-03-08
1
-0
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+7
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clk: tegra: Add la clock for Tegra210
Peter De Schrijver
2018-03-08
1
-0
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+14
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
2017-11-18
13
-66
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+102
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clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()
Nicolin Chen
2017-11-01
1
-2
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+2
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clk: tegra: dfll: Fix drvdata overwriting issue
Nicolin Chen
2017-11-01
3
-13
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+11
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clk: tegra: Fix cclk_lp divisor register
Michał Mirosław
2017-11-01
1
-1
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+1
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clk: tegra: Bump SCLK clock rate to 216 MHz
Dmitry Osipenko
2017-11-01
1
-1
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+1
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clk: tegra: Use common definition of APBDMA clock gate
Dmitry Osipenko
2017-11-01
1
-5
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+1
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clk: tegra: Correct parent of the APBDMA clock
Dmitry Osipenko
2017-11-01
1
-1
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+1
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clk: tegra: Add AHB DMA clock entry
Dmitry Osipenko
2017-11-01
4
-0
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+4
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clk: tegra: Mark APB clock as critical
Jon Hunter
2017-11-01
1
-1
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+1
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clk: tegra: Make tegra_clk_pll_params __ro_after_init
Bhumika Goyal
2017-10-19
1
-8
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+8
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clk: tegra: Fix sor1_out clock implementation
Thierry Reding
2017-10-19
2
-16
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+47
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clk: tegra: Use tegra_clk_register_periph_data()
Thierry Reding
2017-10-19
4
-13
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+4
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clk: tegra: Add peripheral clock registration helper
Thierry Reding
2017-10-19
2
-0
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+11
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clk: tegra: Check BPMP response return code
Timo Alho
2017-10-19
1
-5
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+10
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License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Greg Kroah-Hartman
2017-11-02
2
-0
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+2
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clk: tegra: Fix Tegra210 PLLU initialization
Alex Frid
2017-08-24
1
-2
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+4
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clk: tegra: Correct Tegra210 UTMIPLL poweron delay
Alex Frid
2017-08-24
1
-3
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+3
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clk: tegra: Fix T210 PLLRE registration
Alex Frid
2017-08-24
1
-20
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+1
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clk: tegra: Update T210 PLLSS (D2/DP) registration
Alex Frid
2017-08-24
1
-39
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+9
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clk: tegra: Re-factor T210 PLLX registration
Alex Frid
2017-08-24
4
-49
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+10
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clk: tegra: don't warn for pll_d2 defaults unnecessarily
Peter De Schrijver
2017-08-24
1
-2
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+4
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clk: tegra: change post IDDQ release delay to 5us
Peter De Schrijver
2017-08-24
1
-1
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+1
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clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2C
Alex Frid
2017-08-24
1
-1
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+2
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clk: tegra: Fix T210 effective NDIV calculation
Alex Frid
2017-08-24
1
-4
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+5
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clk: tegra: Init cfg structure in _get_pll_mnp
Peter De Schrijver
2017-08-24
1
-0
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+2
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clk: tegra210: remove non-existing VFIR clock
Peter De Schrijver
2017-08-24
1
-1
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+0
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clk: tegra: disable SSC for PLL_D2
Peter De Schrijver
2017-08-24
1
-1
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+1
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clk: tegra: Enable PLL_SS for Tegra210
Peter De Schrijver
2017-08-24
1
-1
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+1
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