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path: root/drivers/clk/zte/clk-zx296718.c
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* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner2019-06-191-4/+1Star
* clk: zte: constify clk_div_tableArvind Yadav2017-08-311-3/+3
* clk: zx296718: export I2S mux clocksShawn Guo2017-06-201-4/+4
* clk: zte: Mark pll config tables as constStephen Boyd2017-04-121-2/+2
* clk: zte: add pll_vga clock for zx296718Shawn Guo2017-04-121-0/+24
* clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocksShawn Guo2017-04-121-3/+3
* clk: zte: add i2s clocks for zx296718Baoyou Xie2017-02-101-0/+4
* clk: zte: add audio clocks for zx296718Jun Nie2017-01-101-0/+127
* clk: zx296718: do not panic on failureShawn Guo2017-01-101-9/+18
* clk: zx296718: register driver earlier with core_initcallShawn Guo2016-09-231-1/+5
* clk: zx: fix pointer case warningsArnd Bergmann2016-09-171-10/+10
* clk: zx296718: use builtin_platform_driver to simplify the codeWei Yongjun2016-09-171-5/+1Star
* clk: zx: register ZX296718 clocksJun Nie2016-09-141-0/+924