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* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner2019-06-191-4/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* clk: zte: pd_bit is not 0 on zx296718Shawn Guo2017-04-121-1/+11
| | | | | | | | | | | | | | | The bit 0 of PLL_CFG0 register is not powerdown on zx296718, but part of of postdiv2 field. The consequence is that functions like hw_to_idx() and zx_pll_enable() will end up tampering the postdiv2 of the PLL. Let's fix it by defining pd_bit 0xff which is obviously invalid for a bit position and having PLL driver check the validity before operating on the bit. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* clk: zte: add audio clocks for zx296718Jun Nie2017-01-101-0/+127
| | | | | | | | | | | The audio related clock support is missing from the existing zx296718 clock driver. Let's add it, so that the upstream ZX SPDIF driver can work for HDMI audio support. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> [sboyd@codeaurora.org: Staticize some more structures] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: zx: reform pll config info to ease code extensionJun Nie2016-09-141-9/+12
| | | | | | | | Add power down bit and pll lock bit in pll config structure to ease new SoC support. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: zx: Add audio div clock method for zx296702Jun Nie2015-07-281-0/+309
Add SPDIF/I2S divider clock method for zx296702 Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>