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* clk: qoriq: Fix checkpatch type ALLOC_WITH_MULTIPLYEmil Medve2015-01-281-2/+2
| | | | | | | | WARNING:ALLOC_WITH_MULTIPLY: Prefer kcalloc over kzalloc with multiply + subclks = kzalloc(sizeof(struct clk *) * count, GFP_KERNEL); Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: qoriq: Fix checkpatch type PARENTHESIS_ALIGNMENTEmil Medve2015-01-281-4/+4
| | | | | | | | | | | | | | | | | | | | | CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis + rc = of_property_read_string_index(np, "clock-output-names", + 0, &clk_name); CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis + pr_err("Could not register clock provider for node:%s\n", + np->name); CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis + rc = of_property_read_string_index(np, "clock-output-names", + i, &clk_name); CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis + pr_err("Could not register clk provider for node:%s\n", + np->name); Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: pxa: add pxa3xx clock driverRobert Jarzmik2015-01-282-0/+365
| | | | | | | | | | | Move pxa25x clock drivers from arch/arm/mach-pxa to driver/clk. In the move : - convert to new clock framework legacy clocks - provide clocks as before for platform data based boards - provide clocks through devicetree with clk-pxa-dt Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: zynq: Force CPU_2X clock to be ungatedSoren Brinkmann2015-01-281-0/+1
| | | | | | | | | | | | The CPU_2X clock does not have a classical in-kernel user, but is, amongst other things, required for OCM and debug access. Make sure this clock is not mistakenly disabled during boot up by enabling it in the platform's clock driver. Cc: stable@vger.kernel.org # 3.11+ Fixes: 0ee52b157b8e 'clk: zynq: Add clock controller driver' Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* Merge tag 'sunxi-clocks-for-3.20' of ↵Michael Turquette2015-01-288-143/+710
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Allwinner clock changes for 3.20 The set of clock changes for the 3.20 merge window, with mostly: - Some PLL fixes for the A80 and A31 - The MMC custom phase functions are removed, and moved over to the generic phase API. - Add the A80 MMC clocks Some DT changes slipped here as well, to preserve bisectability.
| * sunxi: clk: Set sun6i-pll1 n_start = 1Hans de Goede2015-01-251-0/+1
| | | | | | | | | | | | | | | | | | | | For all pll-s on sun6i n == 0 means use a multiplier of 1, rather then 0 as it means on sun4i / sun5i / sun7i. n_start = 1 is already correctly set for sun6i pll6, but was missing for pll1, this commit fixes this. Cc: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: rewrite sun9i_a80_get_pll4_factors()Hans de Goede2015-01-251-28/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The old implementation of sun9i_a80_get_pll4_factors() has several issues, it checks against 256 / 512 in various places where it should use 255 / 511, it does the wrong thing for low frequencies which are an even multiple of 6 MHz, e.g. if you ask it for 72 MHz it will result in 144 Mhz, and it does not take into account that n must be at least 12. Moreover it is quite hard to read / follow it. This commit rewrites it to be correct in all cases, and makes it much easier to follow the code / to read. Cc: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: Add driver for A80 MMC config clocks/resetsChen-Yu Tsai2015-01-202-0/+220
| | | | | | | | | | | | | | | | | | | | | | | | | | On the A80 SoC, the 4 mmc controllers each have a separate register controlling their register access clocks and reset controls. These registers in turn share a ahb clock gate and reset control. This patch adds a platform device driver for these controls. It requires both clocks and reset controls to be available, so using CLK_OF_DECLARE might not be the best way. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: Add mod0 and mmc module clock support for A80Chen-Yu Tsai2015-01-191-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The module 0 style clocks, or storage module clocks as named in the official SDK, are almost the same as the module 0 clocks on earlier Allwinner SoCs. The only difference is wider mux register bits. As with earlier Allwinner SoCs, mmc module clocks are a special case of mod0 clocks, with phase controls for 2 child clocks, output and sample. This patch adds support for both. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: Add a common setup function for mmc module clocksChen-Yu Tsai2015-01-141-7/+19
| | | | | | | | | | | | | | | | | | | | | | | | The only difference between module clocks on different platforms is the width of the mux register bits and the valid values, which are passed in through struct factors_data. The phase clocks parts are identical. This patch generalizes the setup function, so most of the code can be reused when adding sun9i support, which has a wider mux register. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: Remove custom phase functionMaxime Ripard2015-01-141-37/+0Star
| | | | | | | | | | | | | | | | | | Now that we don't have any user left for our custom phase function, we can safely remove this hack from the code. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Chen-Yu Tsai <wens@csie.org>
| * clk: sunxi: Rework MMC phase clocksMaxime Ripard2015-01-141-62/+69
| | | | | | | | | | | | | | | | | | | | | | | | Instead of having three different clocks for the main MMC clock and the two phase sub-clocks, which involved having three different drivers sharing the same register, rework it to have the same single driver registering three different clocks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Mike Turquette <mturquette@linaro.org>
| * clk: sunxi: Propagate rate changes to parent for mux clocksChen-Yu Tsai2015-01-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The cpu clock on sunxi machines is just a mux clock, which is normally fed by the main PLL, but can be muxed to the main or low power oscillator. Make the mux clock propagate rate changes to its parent, so we can change the clock rate of the PLL, and thus actually implement rate changing on the cpu clock. This patch also removes the no reparenting limit. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: Make the mod0 clk driver also a platform driverHans de Goede2015-01-061-3/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | With the prcm in sun6i (and some later SoCs) some mod0 clocks are instantiated through the mfd framework, and as such do not work with of_clk_declare, since they do not have registers assigned to them yet at of_clk_declare init time. Silence the error on not finding registers in the of_clk_declare mod0 clk setup method, and also register mod0-clk support as a platform driver to work properly with mfd instantiated mod0 clocks. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: Fix factor clocks usage for sun9i core clocksChen-Yu Tsai2014-12-211-6/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | The sunxi factor clocks usage was changed in clk: sunxi: Give sunxi_factors_register a registers parameter However the sun9i core clocks were not fixed up in that patch, resulting in breakage. This patch fixes that. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: Give sunxi_factors_register a registers parameterHans de Goede2014-12-215-14/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit sunxi_factors_register uses of_iomap(node, 0) to get the clk registers. The sun6i prcm has factor clocks, for which we want to use sunxi_factors_register, but of_iomap(node, 0) does not work for the prcm factor clocks, because the prcm uses the mfd framework, so the registers are not part of the dt-node, instead they are added to the platform_device, as platform_device resources. This commit makes getting the registers the callers duty, so that sunxi_factors_register can be used with mfd instantiated platform device too. While at it also add error checking to the of_iomap calls. This commit also drops the __init function from sunxi_factors_register since platform driver probe functions are not __init. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-dividerChen-Yu Tsai2014-12-211-0/+208
| | | | | | | | | | | | | | | | | | | | This patch unifies the sun6i AHB1 clock, originally supported with separate mux and divider clks. It also adds support for the pre-divider on the PLL6 input, thus allowing the clock to be muxed to PLL6 with proper clock rate calculation. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: Remove ahb1_sdram from sun6i/sun8i protected clocks listChen-Yu Tsai2014-12-211-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ahb1_sdram clock gate is only used for accessing the sdram controller's registers over the bus. It is not used for actually clock the controller or the dram, hence it does not need to be protected. This also gets rid of the problem when the protected ahb1_sdram gate is prepared/enabled while it is still an orphan, and the operation is not propagated to the correct parent. This was confirmed on my A23 tablet and my A31 Hummingbird. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | Merge tag 'v3.20-rockchip-clk1' of ↵Michael Turquette2015-01-281-13/+35
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next The two big changes are the additional of the watchdog clock, which we currently only "fake" as the clock gate control is living in a very strange place, but the watchdog driver needs to read the clock rate from it and the setting of rk3288 plls to slow mode upon suspend. Other than that some more exported clocks and a CLK_SET_RATE_PARENT flag for the uart clocks.
| * | clk: rockchip: add a dummy clock for the watchdog pclk on rk3288Heiko Stuebner2015-01-221-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pclk supplying the watchdog is controlled via the SGRF register area. Currently we don't have any clock-type handling external clock bits like this one. Additionally the SGRF isn't even writable in every boot mode. But still the clock control is available and in the future someone might want to use it. Therefore define a simple clock for the time being so that the watchdog driver can read its rate. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: add PVTM clocks on rk3288huang lin2015-01-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Process-Voltage-Temperatiure Monitor block on RK3288 has two clocks: PVTM_CORE and PVTM_GPU. Signed-off-by: Huang Lin <hl@rock-chips.com> Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: use the clock ID for usbphy480m_srcKever Yang2015-01-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use the clock ID for usbphy480m_src so that we can find this clock node in dts. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: rk3288: Make s2r reliable by switching PLLs to slow modeDoug Anderson2014-12-311-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We've been seeing some crashes at resume time on rk3288-based systems. On some machines they simply never wake up from suspend. Symptoms include: - System clearly got to sleep OK. Power consumption is low, the PWM for the PWM regulator has stopped, and the "global_pwroff" output shows that the system is down. - When system tries to wake up power consumption goes up. - No kernel resume code (which was left in PMU SRAM) ran. We added some basic logging to this code (write to a location in SRAM right at resume time) and didn't see the logging run. It appears that we can fix the problem by slowing down APLL before we suspend. On the system I tested things seemed reliable if I disabled 1.8GHz and 1.7GHz. The Mask ROM itself tries to slow things down (which is why PLLs are in slow mode by the time we get to the kernel), but apparently it is crashing before it even gets there. We'll be super paranoid and not just go down to 1.6GHz but we'll match what the Mask ROM seems to be doing and go into slow mode. We'll also be safe and put all PLLs (not just APLL) into slow mode (well, except DPLL which is needed for SDRAM). We'll even put NPLL into slow mode which the Mask ROM didn't do (not that it's used for much important stuff at early resume time). Note that the old Rockchip reference code did something just like this, though they jammed it into pm.c instead of putting it in the syscore ops of the clock driver. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: Add CLK_SET_RATE_PARENT to sclk_uart clocksDoug Anderson2014-12-211-10/+10
| |/ | | | | | | | | | | | | | | | | We'd like to be able to set the clock rate of the sclk_uart clocks and actually be able to achieve clock rates greater than 24MHz. To do this we need to be able to pass rate changes upward. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | clk: ti: Drop use of clk-private.hStephen Boyd2015-01-273-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | These modules don't need to include clk-private.h. Replace the include with clk.h because these modules are clock consumers and also include clk-provider.h in clk/ti.h because struct clk_hw_omap has a struct clk_hw embedded in it. Cc: Tero Kristo <t-kristo@ti.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* | clk: ux500: Drop use of clk-private.hStephen Boyd2015-01-272-2/+0Star
| | | | | | | | | | | | | | | | | | | | These drivers don't need to include clk-private.h. Remove the include. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* | clk: Export phase functionsMaxime Ripard2015-01-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | The phase setter and getter were not exported until now, which was causing build breakages when callers were compiled as module. Export these two functions. Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* | clk: qcom: Add MSM8960/APQ8064 LPASS clock controller (LCC) driverStephen Boyd2015-01-273-0/+595
| | | | | | | | | | | | | | | | | | Add an LCC driver for MSM8960/APQ8064 that supports the i2s, slimbus, and pcm clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* | clk: qcom: Add IPQ806X LPASS clock controller (LCC) driverRajendra Nayak2015-01-274-0/+495
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an LCC driver for IPQ806x that supports the i2s, S/PDIF, and pcm clocks. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Josh Cartwright <joshc@codeaurora.org> [sboyd@codeaurora.org: Reworded commit text, added Kconfig select, fleshed out Kconfig description a bit more, added pll4 configuration and reworked probe for it, added muxes, split out dt-binding file] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* | clk: qcom: Add simple regmap based muxesStephen Boyd2015-01-273-0/+89
| | | | | | | | | | | | | | | | | | | | | | Add support for muxes that use regmap instead of readl/writel directly. We don't support as many features as clk-mux.c, but this is good enough to support getting and setting parents. Adding a table based lookup can be added in the future if needed. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* | clk: qcom: Add support for regmap divider clocksJosh Cartwright2015-01-273-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | Add support for dividers that use regmap instead of readl/writel. Signed-off-by: Josh Cartwright <joshc@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> [sboyd@codeaurora.org: Switch to using generic divider code, drop enable/disable, reword commit text] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* | clk: divider: Make generic for usage elsewhereStephen Boyd2015-01-271-84/+128
| | | | | | | | | | | | | | | | | | | | Some devices don't use mmio to interact with dividers. Split out the logic from the register read/write parts so that we can reuse the division logic elsewhere. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* | clk: Add __clk_mux_determine_rate_closestStephen Boyd2015-01-271-9/+38
| | | | | | | | | | | | | | | | | | | | Some clock drivers want to find the closest rate on the input of a mux instead of a rate that's less than or equal to the desired rate. Add a generic mux function to support this. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* | clk: Fix debugfs clk removal before initedSrinivas Kandagatla2015-01-271-4/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the clks can be registered & unregistered before the clk related debugfs entries are initialized at late_initcall. In the unregister path checking for only dentry before clk_debug_init() would lead dangling pointers in the debug clk list, because the list is already populated in register path and the clk pointer freed in unregister path. The side effect of not removing it from the list is either a null pointer dereference or if lucky to boot the system, the number of clk entries in debugfs disappear. We could add more checks like if (inited && !clk->dentry) but just removing the check for dentry made more sense as debugfs_remove_recursive() seems to be safe with null pointers. This will ensure that the unregistering clk would be removed from the debug list in all the code paths. Without this patch kernel would crash with log: Unable to handle kernel NULL pointer dereference at virtual address 00000000 pgd = c0204000 [00000000] *pgd=00000000 Internal error: Oops: 5 [#1] SMP ARM Modules linked in: CPU: 1 PID: 1 Comm: swapper/0 Tainted: G B 3.19.0-rc3-00007-g412f9ba-dirty #840 Hardware name: Qualcomm (Flattened Device Tree) task: ed948000 ti: ed944000 task.ti: ed944000 PC is at strlen+0xc/0x40 LR is at __create_file+0x64/0x1dc pc : [<c04ee604>] lr : [<c049f1c4>] psr: 60000013 sp : ed945e40 ip : ed945e50 fp : ed945e4c r10: 00000000 r9 : c1006094 r8 : 00000000 r7 : 000041ed r6 : 00000000 r5 : ed4af998 r4 : c11b5e28 r3 : 00000000 r2 : ed945e38 r1 : a0000013 r0 : 00000000 Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel Control: 10c5787d Table: 8020406a DAC: 00000015 Process swapper/0 (pid: 1, stack limit = 0xed944248) Stack: (0xed945e40 to 0xed946000) 5e40: ed945e7c ed945e50 c049f1c4 c04ee604 c0fc2fa4 00000000 ecb748c0 c11c2b80 5e60: c0beec04 0000011c c0fc2fa4 00000000 ed945e94 ed945e80 c049f3e0 c049f16c 5e80: 00000000 00000000 ed945eac ed945e98 c08cbc50 c049f3c0 ecb748c0 c11c2b80 5ea0: ed945ed4 ed945eb0 c0fc3080 c08cbc30 c0beec04 c107e1d8 ecdf0600 c107e1d8 5ec0: c107e1d8 ecdf0600 ed945f54 ed945ed8 c0208ed4 c0fc2fb0 c026a784 c04ee628 5ee0: ed945f0c ed945ef0 c0f5d600 c04ee604 c0f5d5ec ef7fcc7d c0b40ecc 0000011c 5f00: ed945f54 ed945f10 c026a994 c0f5d5f8 c04ecc00 00000007 ef7fcc95 00000007 5f20: c0e90744 c0dd0884 ed945f54 c106cde0 00000007 c117f8c0 0000011c c0f5d5ec 5f40: c1006094 c100609c ed945f94 ed945f58 c0f5de34 c0208e50 00000007 00000007 5f60: c0f5d5ec be9b5ae0 00000000 c117f8c0 c0af1680 00000000 00000000 00000000 5f80: 00000000 00000000 ed945fac ed945f98 c0af169c c0f5dd2c ed944000 00000000 5fa0: 00000000 ed945fb0 c020f298 c0af168c 00000000 00000000 00000000 00000000 5fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 5fe0: 00000000 00000000 00000000 00000000 00000013 00000000 ebcc6d33 bfffca73 [<c04ee604>] (strlen) from [<c049f1c4>] (__create_file+0x64/0x1dc) [<c049f1c4>] (__create_file) from [<c049f3e0>] (debugfs_create_dir+0x2c/0x34) [<c049f3e0>] (debugfs_create_dir) from [<c08cbc50>] (clk_debug_create_one+0x2c/0x16c) [<c08cbc50>] (clk_debug_create_one) from [<c0fc3080>] (clk_debug_init+0xdc/0x144) [<c0fc3080>] (clk_debug_init) from [<c0208ed4>] (do_one_initcall+0x90/0x1e0) [<c0208ed4>] (do_one_initcall) from [<c0f5de34>] (kernel_init_freeable+0x114/0x1e0) [<c0f5de34>] (kernel_init_freeable) from [<c0af169c>] (kernel_init+0x1c/0xfc) [<c0af169c>] (kernel_init) from [<c020f298>] (ret_from_fork+0x14/0x3c) Code: c0b40ecc e1a0c00d e92dd800 e24cb004 (e5d02000) ---[ end trace b940e45b5e25c1e7 ]--- Fixes: 6314b6796e3c "clk: Don't hold prepare_lock across debugfs creation" Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* | Merge branch 'clk-shmobile-for-3.20' of ↵Michael Turquette2015-01-274-4/+342
|\ \ | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
| * | clk: shmobile: Add R-Car Gen2 ADSP clock supportSergei Shtylyov2015-01-081-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the ADSP clock support to the R-Car generation 2 CPG driver. This clock gets derived from PLL1. The layout of the ADSPCKCR register is similar to those of the clocks supported by the 'clk-div6' driver but the divider encoding is non-linear, so can't be supported by that driver... Based on the original patch by Konstantin Kozhevnikov <konstantin.kozhevnikov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | clk: shmobile: Add R-Car Gen2 RCAN clock supportSergei Shtylyov2015-01-081-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the RCAN clock support to the R-Car generation 2 CPG driver. This clock gets derived from the USB_EXTAL clock, dividing it by 6. The layout of the RCANCKCR register is similar to those of the clocks supported by the 'clk-div6' driver but has no divider field, and so can't be supported by that driver... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | clk: shmobile: r8a73a4 common clock framework implementationUlrich Hecht2015-01-082-0/+242
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Driver for the R8A73A4's clocks that are too specific to be supported by a generic driver. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Michael Turquette <mturquette@linaro.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | clk: shmobile: Add r8a7793 supportHisashi Nakamura2015-01-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | R-Car M2N (r8a7793) clock is handled in R-Car Gen2 clock driver. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | clk: shmobile: div6: Avoid changing divisor in .disable()Geert Uytterhoeven2015-01-081-4/+11
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While DIV6 clocks require the divisor field to be non-zero when stopping the clock, some clocks (e.g. ZB on sh73a0) fail to be re-enabled later if the divisor field is changed when stopping the clock. The reason for this is unknown. To fix this, do not touch the divisor field if it's already non-zero. On kzm9g, the smsc911x Ethernet controller is connected to the sh73a0 Bus State Controller, which is clocked by the ZB clock. Without this fix, if the ZB clock is disabled during system suspend, and re-enabled during resume, the kernel locks up when the smsc911x driver tries to access the Ethernet registers. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* | Merge branch 'clk-has-parent' into clk-nextMichael Turquette2015-01-251-0/+30
|\ \
| * | clk: Introduce clk_has_parent()Thierry Reding2015-01-251-0/+30
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This new function is similar to clk_set_parent(), except that it doesn't actually change the parent. It merely checks that the given parent clock can be a parent for the given clock. A situation where this is useful is to check that a particular setup is valid before switching to it. One specific use-case for this is atomic modesetting in the DRM framework where setting a mode is divided into a check phase where a given configuration is validated before applying changes to the hardware. Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* | ARM: clk: add clk-asm9260 driverOleksij Rempel2015-01-202-0/+349
| | | | | | | | | | | | | | Provide CLK support for Alphascale ASM9260 SoC. Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* | clk: st: STiH410: Fix pdiv and fdiv divisor when setting ratePeter Griffin2015-01-201-4/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Debugging eMMC on upstream kernels it has been noticed that when the targetpack configures MMC0 clock to 200Mhz (required to switch to HS200) then everything works OK. However if the kernel sets the clock rate using clk_set_rate, then the eMMC card initialisation fails with timeouts. Lower clock speeds (the default being 50Mhz) work ok, but they we fail to get good eMMC transfer rates. Looking through the vendor kernel clock driver reveals Giuseppe had already fixed this issue, but the patch hasn't made its way upstream. The issue is fixed by changing the logic to manage the pdiv and fdiv divisors used for setting the rate inside the flexgen driver code. Pdiv is mainly targeted for low freq results, while fdiv should be used for divs =< 64. The other way can lead to 'duty cycle' issues. I have changed the original patch to keep the original behaviour in cases where the div is >64 which matches the original comment and patch description more closely. Although no clocks appear to hit this case currently when booting an upstream kernel. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* | clk: ppc-corenet: rename driver to clk-qoriqTang Yuantian2015-01-203-9/+9
| | | | | | | | | | | | | | | | | | | | | | Freescale introduced new ARM-based socs which using the compatible clock IP block with PowerPC-based socs'. So this driver can be used on both platforms. Updated relevant descriptions and renamed this driver to better represent its meaning and keep the function of driver untouched. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* | clock: redefine variable clocks_per_pll as a struct memberTang Yuantian2015-01-201-7/+15
| | | | | | | | | | | | | | | | | | | | redefine variable clocks_per_pll as a struct member If there are multiple PLL clock nodes, this variable will get overwritten. Redefining it as a struct member can avoid that. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* | Merge tag 'for-v3.20-exynos7-clk' of git://linuxtv.org/snawrocki/samsung ↵Michael Turquette2015-01-201-2/+406
|\ \ | | | | | | | | | | | | | | | | | | into clk-next - Clock definitions for Exynos7 SoC peripheral devices: video scaler, USB, DMA, SPI and the audio subsystem.
| * | clk: samsung: exynos7: add clocks for audio blockPadmavathi Venna2015-01-151-2/+141
| | | | | | | | | | | | | | | | | | | | | | | | Add required clk support for I2S, PCM and SPDIF. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Reviewed-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * | clk: samsung: exynos7: add clocks for SPI blockPadmavathi Venna2015-01-151-0/+73
| | | | | | | | | | | | | | | | | | | | | Add clock support for 5 SPI channels. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * | clk: samsung: exynos7: add gate clock for DMA blockPadmavathi Venna2015-01-151-0/+4
| | | | | | | | | | | | | | | | | | | | | Add support for PDMA0 and PDMA1 gate clks. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-05 17:27:18 +0200