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| | | | * | | clk: imx: Switch wrappers to clk_hw based APIAbel Vesa2019-06-071-26/+65
| | | | * | | clk: imx: clk-fixup-mux: Switch to clk_hw based APIAbel Vesa2019-06-072-5/+13
| | | | * | | clk: imx: clk-fixup-div: Switch to clk_hw based APIAbel Vesa2019-06-072-7/+15
| | | | * | | clk: imx: clk-gate-exclusive: Switch to clk_hw based APIAbel Vesa2019-06-072-7/+15
| | | | * | | clk: imx: clk-pfd: Switch to clk_hw based APIAbel Vesa2019-06-072-6/+13
| | | | * | | clk: imx: clk-pllv3: Switch to clk_hw based APIAbel Vesa2019-06-072-6/+13
| | | | * | | clk: imx: clk-gate2: Switch to clk_hw based APIAbel Vesa2019-06-072-6/+15
| | | | * | | clk: imx: clk-cpu: Switch to clk_hw based APIAbel Vesa2019-06-072-6/+13
| | | | * | | clk: imx: clk-busy: Switch to clk_hw based APIAbel Vesa2019-06-072-12/+29
| | | | * | | clk: imx6q: Do not reparent uninitialized IMX6QDL_CLK_PERIPH2 clockAbel Vesa2019-06-071-8/+0Star
| | | | * | | clk: imx6sx: Do not reparent to unregistered IMX6SX_CLK_AXIAbel Vesa2019-06-071-2/+0Star
| | | | * | | clk: imx: Add imx_obtain_fixed_clock clk_hw based variantAbel Vesa2019-06-072-0/+14
| | | | * | | clk: imx: imx8mm: correct audio_pll2_clk to audio_pll2_outPeng Fan2019-06-071-3/+3
| | | | * | | clk: imx: keep the mmdc p1 ipg clock always on on 6sx/ul/ull/sllJacky Bai2019-05-233-3/+3
| | | | * | | clk: imx8mm: Mark dram_apb criticalLeonard Crestez2019-05-231-1/+1
| | | | * | | clk: imx7ulp: update nic1_bus_clk parent infoAnson Huang2019-05-231-1/+1
| | | | * | | clk: imx: Use imx_mmdc_mask_handshake() API for masking MMDC channelAnson Huang2019-05-235-26/+5Star
| | | | * | | clk: imx: Add common API for masking MMDC handshakeAnson Huang2019-05-232-0/+16
| | | | * | | clk: imx8m: Add GIC clockLeonard Crestez2019-05-232-0/+8
| | | | * | | clk: imx8mm: add SNVS clock to clock treeAnson Huang2019-05-231-0/+1
| | | | * | | clk: imx8mq: add SNVS clock to clock treeAnson Huang2019-05-221-0/+1
| | | | * | | clk: imx8mm: add GPIO clocks to clock treeAnson Huang2019-05-201-0/+5
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| | | * | | clk: samsung: Add bus clock for GPU/G3D on Exynos4412Krzysztof Kozlowski2019-06-191-0/+1
| | | * | | clk: samsung: add new clocks for DMC for Exynos5422 SoCLukasz Luba2019-06-061-6/+55
| | | * | | clk: samsung: add BPLL rate table for Exynos 5422 SoCLukasz Luba2019-06-061-1/+16
| | | * | | clk: samsung: exynos5433: Use of_clk_get_parent_count()Kefeng Wang2019-05-301-2/+2
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| | * | | clk: keystone: sci-clk: extend clock IDs to 32 bitsTero Kristo2019-06-071-8/+28
| | * | | clk: keystone: sci-clk: probe clocks from DT instead of firmwareTero Kristo2019-06-072-0/+141
| | * | | clk: keystone: sci-clk: split out the fw clock parsing to own functionTero Kristo2019-06-071-27/+41
| | * | | clk: keystone: sci-clk: cut down the clock name lengthTero Kristo2019-06-071-4/+3Star
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| *-------. \ \ Merge branches 'clk-qcom-gdsc-warn', 'clk-ingenic', 'clk-qcom-qcs404-reset', ...Stephen Boyd2019-07-1222-161/+1285
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| | | | | | * | | clk: meson: g12a: mark fclk_div3 as criticalNeil Armstrong2019-06-111-0/+10
| | | | | | * | | clk: meson: g12a: Add support for G12B CPUB clocksNeil Armstrong2019-06-112-1/+801
| | | | | | * | | clk: meson-g12a: add temperature sensor clocksGuillaume La Roque2019-06-112-1/+33
| | | | | | * | | clk: meson: meson8b: add the cts_i958 clockMartin Blumenstingl2019-06-112-1/+25
| | | | | | * | | clk: meson: meson8b: add the cts_mclk_i958 clocksMartin Blumenstingl2019-06-112-1/+69
| | | | | | * | | clk: meson: meson8b: add the cts_amclk clocksMartin Blumenstingl2019-06-112-1/+69
| | | | | | * | | clk: meson: g12a: add controller register initJerome Brunet2019-05-201-1/+7
| | | | | | * | | clk: meson: eeclk: add init regsJerome Brunet2019-05-202-0/+5
| | | | | | * | | clk: meson: g12a: add mpll register init sequencesJerome Brunet2019-05-201-0/+24
| | | | | | * | | clk: meson: mpll: add init callback and regsJerome Brunet2019-05-202-11/+26
| | | | | | * | | clk: meson: axg: spread spectrum is on mpll2Jerome Brunet2019-05-201-5/+5
| | | | | | * | | clk: meson: gxbb: no spread spectrum on mpll0Jerome Brunet2019-05-201-5/+0Star
| | | | | | * | | clk: meson: mpll: properly handle spread spectrumJerome Brunet2019-05-202-3/+7
| | | | | * | | | clk: xgene: Don't build COMMON_CLK_XGENE by defaultMarc Gonzalez2019-06-121-1/+1
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| | | | * / | | clk: gcc-qcs404: Add PCIe resetsBjorn Andersson2019-06-071-0/+7
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| | | * | | | clk: ingenic: Remove unused functionsPaul Cercueil2019-06-261-73/+0Star
| | | * | | | clk: ingenic: Handle setting the Low-Power Mode bitPaul Cercueil2019-06-267-32/+69
| | | * | | | clk: ingenic: Add missing header in cgu.hPaul Cercueil2019-06-261-0/+1
| | | * | | | clk: ingenic/jz4725b: Fix "pll half" divider not read/written properlyPaul Cercueil2019-06-071-1/+8
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