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path: root/drivers/gpu/drm/i915/i915_reg.h
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| * drm/i915: add S PLL controlEugeni Dodonov2012-04-091-0/+8
| * drm/i915: add PIXCLK_GATE registerEugeni Dodonov2012-04-091-0/+6
| * drm/i915: add SBI registersEugeni Dodonov2012-04-091-0/+12
| * drm/i915: add definition of DDI buffer translations regsEugeni Dodonov2012-04-091-0/+7
| * drm/i915: add definitions for DDI_BUF_CTL registersEugeni Dodonov2012-04-091-0/+23
| * drm/i915: add DP_TP_STATUS registersEugeni Dodonov2012-04-091-0/+8
| * drm/i915: add DP_TP_CTL registersEugeni Dodonov2012-04-091-0/+16
| * drm/i915: add DDI registersEugeni Dodonov2012-04-091-0/+26
| * drm/i915: add enumeration for DDI portsEugeni Dodonov2012-04-091-0/+2
| * drm/i915: add support for power wellsEugeni Dodonov2012-04-091-0/+13
| * drm/i915: ValleyView IRQ supportJesse Barnes2012-03-291-1/+6
| * drm/i915: interrupt bit definitions for VLVJesse Barnes2012-03-291-0/+41
| * drm/i915: add ValleyView specific force wake get/put functionsJesse Barnes2012-03-291-0/+2
| * drm/i915: Enable HDMI on ValleyViewShobhit Kumar2012-03-291-0/+16
| * drm/i915: program drain latency regs on ValleyViewGajanan Bhat2012-03-281-0/+16
| * drm/i915: add ValleyView clock gating initJesse Barnes2012-03-281-0/+18
| * drm/i915: add DPIO supportJesse Barnes2012-03-281-0/+55
| * drm/i915: PLL defines for VLVJesse Barnes2012-03-281-0/+4
| * drm/i915: ValleyView watermark supportJesse Barnes2012-03-281-0/+6
| * drm/i915/intel_i2c: gmbus disabled and reserved ports are invalidDaniel Kurtz2012-03-281-1/+1
| * drm/i915/intel_i2c: assign HDMI port D to pin pair 6Daniel Kurtz2012-03-281-3/+3
| * drm/i915: re-order GT IIR bit definitionsJesse Barnes2012-03-231-6/+14
* | drm/i915: Sanitize BIOS debugging bits from PIPECONFChris Wilson2012-04-011-0/+1
* | Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds2012-03-221-12/+120
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| * \ drm: Merge tag 'v3.3-rc7' into drm-core-nextDave Airlie2012-03-151-0/+15
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| * | drm/i915: add missing SDVO bits for interlaced modes on ILKPaulo Zanoni2012-02-141-0/+1
| * | drm/i915: use gtfifodbgBen Widawsky2012-02-121-0/+6
| * | drm/i915: set interlaced bits for TRANSCONFPaulo Zanoni2012-02-101-0/+2
| * | drm/i915: correctly program the VSYNCSHIFT registerDaniel Vetter2012-02-101-0/+8
| * | drm/i915: clean up interlaced pipeconf bit definitionsDaniel Vetter2012-02-101-3/+14
| * | drm/i915: ppgtt register definitionsDaniel Vetter2012-02-091-0/+18
| * | drm/i915: initialization/teardown for the aliasing ppgttDaniel Vetter2012-02-091-0/+16
| * | drm/i915: swizzling support for snb/ivbDaniel Vetter2012-02-081-0/+34
| * | drm/i915: add per-ring fault reg to error_stateDaniel Vetter2012-01-291-0/+2
| * | drm/i915: collect more per ring error stateDaniel Vetter2012-01-291-0/+3
| * | drm/i915: refactor ring error state capture to use arraysDaniel Vetter2012-01-291-8/+3Star
| * | drm/i915: set AUD_CONFIG N_value_index for DisplayPortWu Fengguang2012-01-291-0/+12
| * | drm/i915: Correct the bit number for the MI_FLUSH_ENABLE.Eric Anholt2012-01-261-1/+1
* | | drm/i915: fix color order for BGR formats on SNBJesse Barnes2012-03-071-1/+1
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* | drm/i915: gen7: Disable the RHWO optimization as it can cause GPU hangs.Kenneth Graunke2012-02-101-0/+3
* | drm/i915: gen7: work around a system hang on IVBEugeni Dodonov2012-02-101-0/+4
* | drm/i915: gen7: Implement an L3 caching workaround.Eugeni Dodonov2012-02-101-0/+7
* | drm/i915: gen7: implement rczunit workaroundEugeni Dodonov2012-02-101-0/+1
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* drm/i915: Add support for resetting the SO write pointers on gen7.Eric Anholt2012-01-031-0/+6
* drm/i915: Set two chicken bits implicated in missed IRQs on Ivybridge.Eric Anholt2012-01-031-0/+4
* drm/i915: add color key support v4Jesse Barnes2012-01-031-0/+3
* drm/i915: add SNB and IVB video sprite support v6Jesse Barnes2012-01-031-0/+133
* drm/i915: drpc debugfs update for gen6Ben Widawsky2012-01-031-0/+8
* drm/i915: Update GEN6_RP_CONTROL definitionsBen Widawsky2012-01-031-1/+5
* drm/i915: Force sync command ordering (Gen6+)Ben Widawsky2012-01-031-0/+1
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