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path: root/drivers/gpu/drm/i915/i915_reg.h
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* drm/i915: enable display messages to GT on ValleyViewJesse Barnes2012-06-201-2/+2
* drm/i915: add HDMI and DP port enumeration on ValleyViewJesse Barnes2012-06-201-1/+0Star
* drm/i915: Enable DP panel power sequencing for ValleyViewShobhit Kumar2012-06-201-0/+13
* drm/i915: ValleyView mode setting limits and PLL functionsJesse Barnes2012-06-201-0/+1
* drm/i915: add L3 bank clock gating disable on VLVJesse Barnes2012-06-181-0/+3
* drm/i915: add TDL unit clock gating disable for VLVJesse Barnes2012-06-181-0/+1
* drm/i915: disable RCBP and VDS unit clock gating on SNB and VLVJesse Barnes2012-06-181-0/+1
* drm/i915: PIPE_CONTROL_TLB_INVALIDATEBen Widawsky2012-06-141-0/+1
* drm/i915: Ivybridge MI_ARB_ON_OFF context w/aBen Widawsky2012-06-141-0/+3
* drm/i915: CXT_SIZE register offsets addedBen Widawsky2012-06-141-0/+21
* drm/i915: clear up backlight #define confusion on gen4+Daniel Vetter2012-06-121-20/+35
* drm/i915: pnv has a backlight polarity control bit, tooDaniel Vetter2012-06-121-0/+2
* drm/i915: remap l3 on hw initBen Widawsky2012-05-311-0/+3
* drm/i915: Dynamic Parity Detection handlingBen Widawsky2012-05-311-0/+17
* drm/i915: explicitly disable the DIPs we're not usingPaulo Zanoni2012-05-301-0/+6
* drm/i915: SDVO hotplug have different interrupt status bits for i915/i965/g4xChris Wilson2012-05-211-3/+8
* drm/i915: Inspect the right status bits for DP/HDMI hotplug on gen4Chris Wilson2012-05-211-6/+15
* drm/i915: implement hsw_write_infoframePaulo Zanoni2012-05-201-0/+4
* drm/i915: add new Haswell DIP controls registersEugeni Dodonov2012-05-191-0/+36
* drm/i915: set the DIP port on ibx_write_infoframePaulo Zanoni2012-05-081-0/+1
* drm/i915: mask the video DIP frequency when changing itPaulo Zanoni2012-05-081-0/+1
* drm/i915: mask the video DIP port selectPaulo Zanoni2012-05-081-0/+1
* drm/i915: DSL_LINEMASK is 12 bits only on gen2Paulo Zanoni2012-05-081-1/+2
* drm/i915: Support pageflipping interrupts for all 3-pipes on IVBChris Wilson2012-05-061-2/+5
* drm/i915: also reset the media engine on gen4/5Daniel Vetter2012-05-051-0/+1
* drm/i915: use the new masked bit macro some moreDaniel Vetter2012-05-031-2/+0Star
* drm/i915: create macros to handle masked bitsDaniel Vetter2012-05-031-5/+3Star
* drm/i915: manage PCH PLLs separately from pipesJesse Barnes2012-05-031-3/+3
* drm/i915: [GEN7] Use HW scheduler for fixed function shadersBen Widawsky2012-04-181-0/+15
* drm/i915: Replace open coded MI_BATCH_GTTChris Wilson2012-04-181-0/+1
* drm/i915: Mask reserved bits in display/sprite address registersArmin Reese2012-04-171-0/+7
* drm/i915: add WRPLL divider programming bitsEugeni Dodonov2012-04-171-0/+4
* drm/i915: add definition of LPT FDI port width registersEugeni Dodonov2012-04-171-0/+3
* drm/i915: set stc evict disable lra evict w/aDaniel Vetter2012-04-171-0/+1
* drm/i915: implement w/a for incorrect guarband clippingDaniel Vetter2012-04-171-0/+1
* drm/i915: properly set ppgtt cacheability on snbDaniel Vetter2012-04-171-0/+4
* drm/i915: set w/a bit for snb pagefaultsDaniel Vetter2012-04-171-0/+3
* drm/i915: implement a media hang w/aDaniel Vetter2012-04-171-0/+1
* Merge tag 'v3.4-rc3' into drm-intel-next-queuedDaniel Vetter2012-04-171-0/+3
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| * drm/i915: implement ColorBlt w/aDaniel Vetter2012-04-111-0/+3
* | drm/i915: add rc6 residency times to debugfsBen Widawsky2012-04-121-0/+5
* | Merge branch 'drm-intel-next' of git://people.freedesktop.org/~danvet/drm-int...Dave Airlie2012-04-121-11/+363
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| * drm/i915: dump the DMA fetch addr register on pre-gen6Daniel Vetter2012-04-091-0/+1
| * drm/i915: ring irq cleanupsBen Widawsky2012-04-091-4/+8
| * drm/i915: add SFUSE_STRAP registers for digital port detectionEugeni Dodonov2012-04-091-0/+7
| * drm/i915: add WM_LINETIME registersEugeni Dodonov2012-04-091-0/+10
| * drm/i915: add WRPLL clocksEugeni Dodonov2012-04-091-0/+8
| * drm/i915: add LCPLL control registersEugeni Dodonov2012-04-091-0/+7
| * drm/i915: add SSC offsets for SBI accessEugeni Dodonov2012-04-091-0/+15
| * drm/i915: add port clock selection support for HSWEugeni Dodonov2012-04-091-0/+23
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