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path: root/drivers/gpu/drm/i915/intel_color.c
Commit message (Expand)AuthorAgeFilesLines
* drm/i915: move modesetting core code under display/Jani Nikula2019-06-171-1428/+0Star
* drm/i915/icl: Add Multi-segmented gamma supportShashank Sharma2019-06-171-4/+122
* drm/i915: Rename ivb_load_lut_10_maxShashank Sharma2019-06-171-7/+7
* drm/i915: Introduce vfunc read_luts() to create hw lutSwati Sharma2019-06-051-0/+8
* drm/i915: Add debugs for the C8 vs. legacy LUT caseVille Syrjälä2019-05-281-1/+3
* drm/i915: Clean up cherryview_load_luts()Ville Syrjälä2019-04-261-37/+59
* drm/i915: Fix ICL output CSC programmingVille Syrjälä2019-04-261-3/+3
* drm/i915: extract intel_color.h from intel_drv.hJani Nikula2019-04-081-0/+1
* drm/i915: Expose full 1024 LUT entries on ivb+Ville Syrjälä2019-04-031-42/+33Star
* drm/i915: Add "10.6" LUT mode for i965+Ville Syrjälä2019-04-031-1/+61
* drm/i915: Add 10bit LUT for ilk/snbVille Syrjälä2019-04-031-10/+39
* drm/i915: Implement split/10bit gamma for ivb/hswVille Syrjälä2019-04-031-21/+92
* drm/i915: Don't use split gamma when we don't have toVille Syrjälä2019-04-031-95/+90Star
* drm/i915: Extract ilk_lut_10()Ville Syrjälä2019-04-031-16/+11Star
* drm/i915: Program EXT2 GC MAX registersUma Shankar2019-03-291-0/+22
* drm/i915: Fix GCMAX color register programmingUma Shankar2019-03-291-11/+11
* drm/i915: Skip the linear degamma LUT load on ICL+Ville Syrjälä2019-03-281-27/+64
* drm/i915: Drop the pointless linear legacy LUT load on CHVVille Syrjälä2019-03-281-16/+1Star
* drm/i915: Extract ilk_color_check()Ville Syrjälä2019-03-281-43/+33Star
* drm/i915: Extract bdw_color_check()Ville Syrjälä2019-03-281-0/+39
* drm/i915: Extract glk_color_check()Ville Syrjälä2019-03-281-0/+40
* drm/i915: Extract icl_color_check()Ville Syrjälä2019-03-281-17/+53
* drm/i915: Extract chv_color_check()Ville Syrjälä2019-03-281-4/+36
* drm/i915: Extract i9xx_color_check()Ville Syrjälä2019-03-281-5/+28
* drm/i915: Turn intel_color_check() into a vfuncVille Syrjälä2019-03-281-10/+20
* drm/i915: Extract check_luts()Ville Syrjälä2019-03-281-28/+40
* drm/i915: Fix legacy gamma mode for ICLVille Syrjälä2019-03-181-0/+3
* drm/i915: Split ilk vs. icl csc matrix handlingVille Syrjälä2019-03-151-29/+42
* drm/i915: Clean the csc limited range/identity programmingVille Syrjälä2019-03-151-26/+27
* drm/i915: Extract ilk_csc_convert_ctm()Ville Syrjälä2019-03-151-44/+53
* drm/i915: Clean up ilk/icl pipe/output CSC programmingVille Syrjälä2019-03-151-86/+82Star
* drm/i915: Extract ilk_csc_limited_range()Ville Syrjälä2019-03-151-8/+14
* drm/i915: Precompute/readout/check CHV CGM modeVille Syrjälä2019-03-151-7/+21
* drm/i915: Readout and check csc_modeVille Syrjälä2019-03-151-2/+2
* drm/i915/gen11+: First assume next platforms will inherit stuffRodrigo Vivi2019-03-131-1/+1
* drm/i915/icl: Enable pipe output cscUma Shankar2019-02-131-19/+58
* drm/i915/icl: Enable ICL Pipe CSC blockUma Shankar2019-02-131-1/+4
* drm/i915/icl: Add icl pipe degamma and gamma supportUma Shankar2019-02-131-2/+19
* drm/i915/glk: Fix degamma lut programmingUma Shankar2019-02-131-28/+34
* drm/i915: Update DSPCNTR gamma/csc bits during crtc_enable()Ville Syrjälä2019-02-081-0/+4
* drm/i915: Disable pipe gamma when C8 pixel format is usedVille Syrjälä2019-02-081-1/+7
* drm/i915: Turn off pipe CSC when it's not neededVille Syrjälä2019-02-081-2/+8
* drm/i915: Turn off pipe gamma when it's not neededVille Syrjälä2019-02-081-2/+53
* drm/i915: Track pipe csc enable in crtc stateVille Syrjälä2019-02-081-1/+6
* drm/i915: Track pipe gamma enable/disable in crtc stateVille Syrjälä2019-02-081-1/+27
* drm/i915: Populate gamma_mode for all platformsVille Syrjälä2019-02-081-15/+45
* drm/i915: Move LUT programming to happen after vblank waitsVille Syrjälä2019-02-071-24/+1Star
* drm/i915: Split color mgmt based on single vs. double buffered registersVille Syrjälä2019-02-071-26/+23Star
* drm/i915: Pull GAMMA_MODE write out from haswell_load_luts()Ville Syrjälä2019-02-071-16/+20
* drm/i915: Constify the state arguments to the color management stuffVille Syrjälä2019-02-071-64/+76
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