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path: root/drivers/gpu/drm/i915/intel_dpll_mgr.c
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* drm/i915: switch intel_wait_for_register to uncoreDaniele Ceraolo Spurio2019-03-261-12/+13
* drm/i915/ehl: Add dpll mgrLucas De Marchi2019-03-221-1/+15
* drm/i915: Remove the fragile array index -> link rate mappingVille Syrjälä2019-03-191-68/+68
* drm/i915: Nuke icl_calc_dp_combo_pll_link()Ville Syrjälä2019-03-191-70/+0Star
* drm/i915: Remove redundant on stack dpll_hw_state from icl_get_dpll()Ville Syrjälä2019-03-191-18/+17Star
* drm/i915: Pass crtc_state down to icl dpll funcsVille Syrjälä2019-03-191-4/+8
* drm/i915: Remove redundant on stack dpll_hw_state from cnl_get_dpll()Ville Syrjälä2019-03-191-8/+7Star
* drm/i915: Pass crtc_state down to cnl dpll funcsVille Syrjälä2019-03-191-17/+12Star
* drm/i915: Remove redundant on stack dpll_hw_state from bxt_get_dpll()Ville Syrjälä2019-03-191-16/+10Star
* drm/i915: Pass crtc_state down to bxt dpll funcsVille Syrjälä2019-03-191-23/+25
* drm/i915: Remove redundant on stack dpll_hw_state from skl_get_dpll()Ville Syrjälä2019-03-191-8/+7Star
* drm/i915: Pass crtc_state down to skl dpll funcsVille Syrjälä2019-03-191-10/+7Star
* drm/i915: Don't pass crtc to intel_get_shared_dpll() and .get_dpll()Ville Syrjälä2019-03-191-29/+27Star
* drm/i915: Don't pass crtc to intel_find_shared_dpll()Ville Syrjälä2019-03-191-9/+9
* drm/i915/icl: remove intel_dpll_is_combophy()Lucas De Marchi2019-03-151-5/+0Star
* drm/i915/icl: split combo and tbt pll funcsLucas De Marchi2019-03-151-20/+54
* drm/i915/icl: split combo and mg pll disableLucas De Marchi2019-03-151-7/+23
* drm/i915/icl: split pll enable in three stepsLucas De Marchi2019-03-151-19/+37
* drm/i915/icl: split combo and mg pll enableLucas De Marchi2019-03-151-4/+21
* drm/i915/gen11+: First assume next platforms will inherit stuffRodrigo Vivi2019-03-131-1/+1
* drm/i915/icl: move MG pll hw_state readoutLucas De Marchi2019-03-021-48/+74
* drm/i915: Pick the first unused PLL once againVille Syrjälä2019-01-311-1/+2
* drm/i915/icl: keep track of unused pll while loopingLucas De Marchi2019-01-291-10/+9Star
* drm/i915/icl: use tc_port in MG_PLL macrosLucas De Marchi2019-01-291-40/+39Star
* drm/i915/dpll_mgr: switch to kernel typesJani Nikula2019-01-171-72/+73
* drm/i915: Markup paired operations on display power domainsChris Wilson2019-01-141-21/+45
* drm/i915/icl: Calculate DPLL params for DSIMadhav Chauhan2018-12-031-1/+2
* drm/i915/icl: Fix crash when getting DPLL of a MST encoder in TC portsJosé Roberto de Souza2018-10-311-2/+10
* drm/i915/icl: Refactor icl pll functionsVandita Kulkarni2018-10-161-37/+17Star
* drm/i915/icl: Use helper functions to classify the portsVandita Kulkarni2018-10-161-10/+4Star
* drm/i915/icl: Refactor get_ddi_pll using helper funcVandita Kulkarni2018-10-161-1/+1
* drm/i915: Fixup kernel doc for param name changesChris Wilson2018-10-081-3/+3
* drm/i915: Make shared dpll functions take crtc_state, v3.Maarten Lankhorst2018-10-051-18/+11Star
* drm/i915: Fix ICL+ HDMI clock readoutVille Syrjälä2018-09-041-8/+15
* drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separa...Manasi Navare2018-08-201-6/+7
* drm/i915/icl: Add TBT checks for PLL calculationsAnusha Srivatsa2018-07-281-1/+3
* Merge drm/drm-next into drm-intel-next-queuedRodrigo Vivi2018-07-231-3/+3
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| * Merge tag 'drm-intel-next-2018-07-09' of git://anongit.freedesktop.org/drm/dr...Dave Airlie2018-07-181-24/+85
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| * | drm/i915: Use drm_plane_mask() & co.Ville Syrjälä2018-07-021-3/+3
* | | drm/i915/icl: compute the TBT PLL registersPaulo Zanoni2018-07-201-1/+21
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* | drm/i915: Mark expected switch fall-throughsGustavo A. R. Silva2018-07-051-0/+3
* | drm/i915/icl: Do read-modify-write as needed during MG PLL programmingImre Deak2018-06-211-4/+35
* | drm/i915/icl: Fix MG PLL setup when refclk is 38.4MHzImre Deak2018-06-211-20/+47
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* drm/i915/icl: start adding the TBT pllPaulo Zanoni2018-06-141-4/+16
* drm/i915/icl: Get DDI clock for ICL based on PLLs.Manasi Navare2018-06-021-0/+70
* drm/i915/icl: compute the MG PLL registersPaulo Zanoni2018-05-081-1/+222
* drm/i915/icl: compute the combo PHY (DPLL) DP registersPaulo Zanoni2018-05-081-1/+86
* drm/i915/icl: compute the combo PHY (DPLL) HDMI registersPaulo Zanoni2018-05-081-3/+36
* drm/i915/icl: add basic support for the ICL clocksPaulo Zanoni2018-05-081-1/+312
* drm/i915: reorder dpll_info membersLucas De Marchi2018-03-271-24/+24
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