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path: root/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
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* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner2019-05-301-9/+1Star
* drm/mediatek: implement connection from BLS to DPI0Bibby Hsieh2018-10-031-1/+13
* drm/mediatek: fix connection from RDMA2 to DSI1Stu Hsieh2018-08-271-1/+1
* drm/mediatek: add connection from RDMA2 to DSI0Stu Hsieh2018-08-271-0/+4
* drm/mediatek: add connection from RDMA1 to DSI0Stu Hsieh2018-08-271-0/+4
* drm/mediatek: add connection from RDMA0 to DSI1Stu Hsieh2018-08-271-0/+4
* drm/mediatek: add connection from RDMA0 to DPI1Stu Hsieh2018-08-271-0/+4
* drm/mediatek: Add support for mediatek SOC MT2712stu.hsieh@mediatek.com2018-06-271-0/+39
* drm/mediatek: add DSI3 support for mutexstu.hsieh@mediatek.com2018-06-241-0/+5
* drm/mediatek: add DSI2 support for mutexstu.hsieh@mediatek.com2018-06-241-0/+5
* drm/mediatek: add DPI1 support for mutexstu.hsieh@mediatek.com2018-06-241-0/+5
* drm/mediatek: add connection from RDMA2 to DSI3stu.hsieh@mediatek.com2018-06-241-0/+8
* drm/mediatek: add connection from RDMA2 to DSI2stu.hsieh@mediatek.com2018-06-241-0/+8
* drm/mediatek: add connection from RDMA2 to DSI1stu.hsieh@mediatek.com2018-06-241-0/+8
* drm/mediatek: add connection from RDMA2 to DPI1stu.hsieh@mediatek.com2018-06-241-0/+8
* drm/mediatek: add connection from RDMA2 to DPI0stu.hsieh@mediatek.com2018-06-241-0/+9
* drm/mediatek: add connection from RDMA1 to DSI3stu.hsieh@mediatek.com2018-06-241-0/+8
* drm/mediatek: add connection from RDMA1 to DSI2stu.hsieh@mediatek.com2018-06-241-0/+9
* drm/mediatek: add connection from RDMA1 to DSI1stu.hsieh@mediatek.com2018-06-241-0/+9
* drm/mediatek: add connection from RDMA1 to DPI1stu.hsieh@mediatek.com2018-06-241-0/+8
* drm/mediatek: add connection from RDMA0 to DSI3stu.hsieh@mediatek.com2018-06-241-0/+4
* drm/mediatek: add connection from RDMA0 to DSI2stu.hsieh@mediatek.com2018-06-241-0/+4
* drm/mediatek: add connection from RDMA0 to DPI0stu.hsieh@mediatek.com2018-06-241-0/+5
* drm/mediatek: Update the definition of connection from RDMA1 to DPI0stu.hsieh@mediatek.com2018-06-241-4/+4
* drm/mediatek: add connection from OD1 to RDMA1stu.hsieh@mediatek.com2018-06-241-0/+4
* drm/mediatek: add ddp component OD1stu.hsieh@mediatek.com2018-06-241-2/+2
* drm/mediatek: add ddp component AAL1stu.hsieh@mediatek.com2018-06-241-1/+1
* drm/mediatek: support maximum 64 mutex modstu.hsieh@mediatek.com2018-06-241-28/+47
* drm/mediatek: add support for Mediatek SoC MT2701yt.shen@mediatek.com2017-04-071-0/+17
* drm/mediatek: update display module connectionsyt.shen@mediatek.com2017-04-071-0/+25
* drm/mediatek: add shadow register supportyt.shen@mediatek.com2017-04-071-0/+25
* drm/mediatek: add *driver_data for different hardware settingsyt.shen@mediatek.com2017-04-071-34/+37
* drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.CK Hu2016-05-061-0/+353