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path: root/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
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* drm/msm/mdp5: Enable 3D mux in mdp5_ctlArchit Taneja2017-04-081-2/+7
* drm/msm/mdp5: Reset CTL blend registers before configuring themArchit Taneja2017-04-081-0/+18
* drm/msm/mdp5: Stage right side hwpipes on Right-side Layer MixerArchit Taneja2017-04-081-4/+8
* drm/msm/mdp5: Add optional 'right' Layer Mixer in CRTC stateArchit Taneja2017-04-081-3/+41
* drm/msm/mdp5: Remove mixer/intf pointers from mdp5_ctlArchit Taneja2017-04-081-31/+37
* drm/msm/mdp5: Remove the pipeline stuff in mdp5_ctlArchit Taneja2017-04-081-25/+17Star
* drm/msm/mdp5: Clean up interface assignmentArchit Taneja2017-04-081-15/+6Star
* drm/msm/mdp5: Start using mdp5_hw_mixerArchit Taneja2017-04-081-18/+20
* drm/msm/mdp5: Misc cursor plane bitsArchit Taneja2017-02-061-2/+8
* drm/msm/mdp5: Prepare CRTC/LM for empty stagesArchit Taneja2017-02-061-2/+2
* drm/msm/mdp5: Use updated MDP5 register namesArchit Taneja2016-07-161-13/+13
* drm/msm/mdp5: Allocate CTL0/1 for dual DSI single FLUSHHai Li2015-08-161-19/+121
* drm/msm/mdp5: Allocate CTL for each display interfaceHai Li2015-08-161-33/+20Star
* drm/msm/mdp5: Add plane blending operation support for MDP5 (v2)jilai wang2015-08-161-5/+61
* drm/msm: Use customized function to wait for atomic commit doneHai Li2015-06-111-2/+9
* drm/msm/mdp5: Remove CTL flush dummy bitsStephane Viau2015-04-021-11/+0Star
* drm/msm/mdp5: Separate MDP5 domain from MDSS domainStephane Viau2015-04-021-10/+10
* drm/msm/mdp5: Add START signal to kick off certain pipelinesStephane Viau2015-04-021-32/+215
* drm/msm/mdp5: Enhance operation mode for pipeline configurationStephane Viau2015-04-021-10/+81
* drm/msm/mdp5: fix parameter type for mdp5_ctl_set_intf()Stephane Viau2015-02-011-1/+1
* drm/msm/mdp5: remove global mdp5_ctl_mgrRob Clark2014-11-211-10/+16
* drm/msm/mdp5: don't use void * for opaque typesRob Clark2014-11-211-23/+14Star
* drm/msm: add multiple CRTC and overlay supportStephane Viau2014-11-211-0/+325