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path: root/drivers/gpu/drm/nouveau/core/engine
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* drm/nvce/mc: fix msi rearm on GF114Sid Boyce2014-01-071-1/+1
* drm/nvc0/gr: fix mthd data submissionKelly Doran2014-01-071-1/+1
* drm/nouveau: populate master subdev pointer only when fully constructedBen Skeggs2014-01-071-0/+2
* drm/nouveau/sw: fix oops if gpu has its display block disabledBen Skeggs2013-12-031-1/+1
* drm/nouveau/clk: Add support for NVAA/NVACRoy Spliet2013-12-031-2/+2
* drm/nouveau/fifo: Hook up pause and resume for NV50 and NV84+Roy Spliet2013-12-032-0/+6
* drm/nvc0-/gr: shift wrapping bug in nvc0_grctx_generate_r406800Dan Carpenter2013-11-141-1/+1
* drm/nvc0-: remove nasty fifo swmthd hack for flip completion methodBen Skeggs2013-11-142-14/+0Star
* drm/nvc8/mc: msi rearm is via the nvc0 methodBen Skeggs2013-11-141-1/+1
* drm/nouveau/fb: implement various bits of work towards memory reclockingBen Skeggs2013-11-081-5/+5
* drm/nouveau/device: initial control object class, with pstate control methodsBen Skeggs2013-11-083-2/+155
* drm/nouveau/clk: implement power state and engine clock control in coreBen Skeggs2013-11-082-15/+15
* drm/nouveau/volt: implement voltage control in coreBen Skeggs2013-11-084-0/+47
* drm/nouveau/perfmon: initial infrastructure to expose performance countersBen Skeggs2013-11-0818-2/+1536
* drm/nouveau/bus: add interfaces/helpers for sequencerBen Skeggs2013-11-081-10/+10
* drm/nouveau/bus: make external class definitions pointersBen Skeggs2013-11-088-63/+63
* drm/nouveau/pwr: initial implementationBen Skeggs2013-11-084-0/+21
* drm/nouveau/fifo: make external class definitions into pointersBen Skeggs2013-11-0816-78/+78
* drm/nouveau/device: recognise GK208Ben Skeggs2013-11-082-13/+48
* drm/nvc0-/gr: fix a number of missing explicit array terminators...Ben Skeggs2013-11-083-0/+6
* drm/nouveau/disp: semi-complete link training sequence even if display disapp...Ben Skeggs2013-11-081-16/+32
* drm/nvd0-/disp: reorder writes to lane current control regsBen Skeggs2013-11-081-4/+8
* drm/nv94-nvc0/disp: reorder writes to lane current control regsBen Skeggs2013-11-081-4/+8
* drm/nouveau/disp: log if DP link training failsBen Skeggs2013-11-081-1/+3
* drm/nvd9-/disp: disable display underflow reporting at initBen Skeggs2013-11-081-0/+9
* drm/nv50-nvaf/fb: split the class definitions up a bitBen Skeggs2013-11-081-13/+13
* drm/nouveau/fb: make external class definitions pointersBen Skeggs2013-11-088-62/+62
* drm/nv50-nv86,nv92/mc: rearm msi via pci config space, rather than mmio mirrorBen Skeggs2013-11-081-2/+2
* drm/nvc0,nvc4/mc: handle 0xc0's "special" msi rearmBen Skeggs2013-11-083-19/+19
* drm/nouveau/mc: store static data in nouveau_mc class definitionBen Skeggs2013-11-088-62/+62
* drm/nouveau/device: use an additional bit from NV_PMC_BOOT_0 to identify chipsetBen Skeggs2013-11-081-3/+3
* drm/nv31/mpeg: remove need for separate refcnt on engine useBen Skeggs2013-11-082-19/+21
* drm/nv31/mpeg: split the nv31 and nv40 dma setting implementationsIlia Mirkin2013-11-083-6/+63
* drm/nv31/mpeg: store chan singleton in engine, use it for dispatchIlia Mirkin2013-11-082-15/+21
* drm/nv40/mpeg: use the nv31-provided classesIlia Mirkin2013-11-083-74/+21Star
* drm/nv44/mpeg: create a copy of the nv31/nv40 implsIlia Mirkin2013-11-082-12/+206
* drm/nv31/mpeg: no need to set compat mode differently for nv44 grIlia Mirkin2013-11-081-5/+1Star
* drm/nv10/kms: add plane support for nv10-nv40Ilia Mirkin2013-11-081-0/+9
* drm/nv10: fix chipset checks, mostly for the benefit of nv1aIlia Mirkin2013-11-082-6/+10
* drm/nv10: introduce a new NV_11 card typeIlia Mirkin2013-11-081-2/+9
* drm/nouveau/vic: rename PUNK1C1 to PVICBen Skeggs2013-11-082-4/+4
* drm/nouveau/core: convert event handler apis to split create/enable semanticsBen Skeggs2013-11-083-54/+51Star
* drm/nv50-/sw: share engine/channel constructor between implementationsBen Skeggs2013-11-083-51/+37Star
* drm/nouveau/sw: prepare for the sharing of constructors between implementationsBen Skeggs2013-11-0813-75/+79
* drm/nv50-/sw: make vblank tracking data private to the implementationsBen Skeggs2013-11-083-18/+25
* drm/nv50-/sw: share engine/channel struct definitions between implementationsBen Skeggs2013-11-083-24/+25
* drm/nv50/disp: prevent false output detection on the original nv50Emil Velikov2013-09-041-5/+10
* drm/nv50-/disp: use the number of dac, sor, pior rather than hardcoded valuesEmil Velikov2013-09-041-17/+17
* drm/nouveau: remove duplicate copy of nv44_graph_classIlia Mirkin2013-09-041-0/+3
* drm/nouveau/vdec: implement support for VP3 enginesIlia Mirkin2013-09-044-52/+101
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