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path: root/drivers/gpu/drm/nouveau/core/engine
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* drm/nouveau/disp: add a method to fetch info needed by drm vblank timestampingBen Skeggs2014-01-299-7/+124
* drm/nv50/gr: print mpc trap name when it's not an mp trapIlia Mirkin2014-01-231-0/+20
* drm/nv50/gr: update list of mp errors, make it a bitfieldIlia Mirkin2014-01-231-8/+10
* drm/nv50/gr: add more trap names to print on errorIlia Mirkin2014-01-231-58/+70
* drm/nouveau/devinit: lock/unlock crtc regs for all devices, not just pre-nv50Ilia Mirkin2014-01-231-2/+7
* drm/nv50-/devinit: prevent use of engines marked as disabled by hw/vbiosIlia Mirkin2014-01-236-31/+10Star
* drm/nouveau/devinit: tidy up the subdev class definitionBen Skeggs2014-01-238-63/+63
* drm/nouveau/bar: tidy up the subdev and object class definitionsBen Skeggs2014-01-232-0/+2
* drm/nouveau/instmem: tidy up the subdev class definitionBen Skeggs2014-01-238-63/+63
* drm/nve0/fifo: recover from mmu faults on bar1/bar3Ben Skeggs2014-01-231-11/+20
* drm/nve0/fifo: keep mmu fault interrupts enabled at all timesBen Skeggs2014-01-231-1/+16
* drm/nve0/fifo: update human-readable mmu fault descriptionsBen Skeggs2014-01-231-11/+87
* drm/nve0/fifo: document more intr status bitsBen Skeggs2014-01-231-5/+72
* drm/nve0/fifo: populate PBDMA status bitfield with more definitionsBen Skeggs2014-01-231-2/+30
* drm/nve0/fifo: s/subfifo/PBDMA/Ben Skeggs2014-01-231-15/+15
* drm/nve0/fifo: s/playlist/runlist/Ben Skeggs2014-01-231-14/+20
* drm/nvf0/gr: enable acceleration with our chsw ucodeBen Skeggs2014-01-231-1/+1
* drm/nv108/gr: enable acceleration with our chsw ucodeBen Skeggs2014-01-231-1/+1
* drm/nvc0-/gr: handle fwmthd interrupts in ucodeBen Skeggs2014-01-237-294/+308
* drm/nvc0-/gr: fiddle some magic around strand initBen Skeggs2014-01-237-1110/+1191
* drm/nv108/gr: initial support (need external fuc)Ben Skeggs2014-01-2311-10/+3071
* drm/nv108/ce: enable copy enginesBen Skeggs2014-01-231-1/+1
* drm/nv108/fifo: initial supportBen Skeggs2014-01-234-55/+113
* drm/nvf0/gr: remove a copy+pasto in ctx reglistBen Skeggs2014-01-231-1/+0Star
* drm/nvc0-/gr: bring in some macros to abstract falcon isa differencesBen Skeggs2014-01-2312-3943/+4431
* drm/nouveau/falcon: use vmalloc to create firwmare copiesIlia Mirkin2014-01-231-5/+15
* drm/nvce/mc: fix msi rearm on GF114Sid Boyce2014-01-071-1/+1
* drm/nvc0/gr: fix mthd data submissionKelly Doran2014-01-071-1/+1
* drm/nouveau: populate master subdev pointer only when fully constructedBen Skeggs2014-01-071-0/+2
* drm/nouveau/sw: fix oops if gpu has its display block disabledBen Skeggs2013-12-031-1/+1
* drm/nouveau/clk: Add support for NVAA/NVACRoy Spliet2013-12-031-2/+2
* drm/nouveau/fifo: Hook up pause and resume for NV50 and NV84+Roy Spliet2013-12-032-0/+6
* drm/nvc0-/gr: shift wrapping bug in nvc0_grctx_generate_r406800Dan Carpenter2013-11-141-1/+1
* drm/nvc0-: remove nasty fifo swmthd hack for flip completion methodBen Skeggs2013-11-142-14/+0Star
* drm/nvc8/mc: msi rearm is via the nvc0 methodBen Skeggs2013-11-141-1/+1
* drm/nouveau/fb: implement various bits of work towards memory reclockingBen Skeggs2013-11-081-5/+5
* drm/nouveau/device: initial control object class, with pstate control methodsBen Skeggs2013-11-083-2/+155
* drm/nouveau/clk: implement power state and engine clock control in coreBen Skeggs2013-11-082-15/+15
* drm/nouveau/volt: implement voltage control in coreBen Skeggs2013-11-084-0/+47
* drm/nouveau/perfmon: initial infrastructure to expose performance countersBen Skeggs2013-11-0818-2/+1536
* drm/nouveau/bus: add interfaces/helpers for sequencerBen Skeggs2013-11-081-10/+10
* drm/nouveau/bus: make external class definitions pointersBen Skeggs2013-11-088-63/+63
* drm/nouveau/pwr: initial implementationBen Skeggs2013-11-084-0/+21
* drm/nouveau/fifo: make external class definitions into pointersBen Skeggs2013-11-0816-78/+78
* drm/nouveau/device: recognise GK208Ben Skeggs2013-11-082-13/+48
* drm/nvc0-/gr: fix a number of missing explicit array terminators...Ben Skeggs2013-11-083-0/+6
* drm/nouveau/disp: semi-complete link training sequence even if display disapp...Ben Skeggs2013-11-081-16/+32
* drm/nvd0-/disp: reorder writes to lane current control regsBen Skeggs2013-11-081-4/+8
* drm/nv94-nvc0/disp: reorder writes to lane current control regsBen Skeggs2013-11-081-4/+8
* drm/nouveau/disp: log if DP link training failsBen Skeggs2013-11-081-1/+3
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