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* Merge tag 'gpio-v4.20-1' of ↵Linus Torvalds2018-10-231-42/+37Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull GPIO updates from Linus Walleij: "This is the bulk of GPIO changes for the v4.20 series: Core changes: - A patch series from Hans Verkuil to make it possible to enable/disable IRQs on a GPIO line at runtime and drive GPIO lines as output without having to put/get them from scratch. The irqchip callbacks have been improved so that they can use only the fastpatch callbacks to enable/disable irqs like any normal irqchip, especially the gpiod_lock_as_irq() has been improved to be callable in fastpath context. A bunch of rework had to be done to achieve this but it is a big win since I never liked to restrict this to slowpath. The only call requireing slowpath was try_module_get() and this is kept at the .request_resources() slowpath callback. In the GPIO CEC driver this is a big win sine a single line is used for both outgoing and incoming traffic, and this needs to use IRQs for incoming traffic while actively driving the line for outgoing traffic. - Janusz Krzysztofik improved the GPIO array API to pass a "cookie" (struct gpio_array) and a bitmap for setting or getting multiple GPIO lines at once. This improvement orginated in a specific need to speed up an OMAP1 driver and has led to a much better API and real performance gains when the state of the array can be used to bypass a lot of checks and code when we want things to go really fast. The previous code would minimize the number of calls down to the driver callbacks assuming the CPU speed was orders of magnitude faster than the I/O latency, but this assumption was wrong on several platforms: what we needed to do was to profile and improve the speed on the hot path of the array functions and this change is now completed. - Clean out the painful and hard to grasp BNF experiments from the device tree bindings. Future approaches are looking into using JSON schema for this purpose. (Rob Herring is floating a patch series.) New drivers: - The RCAR driver now supports r8a774a1 (RZ/G2M). - Synopsys GPIO via CREGs driver. Major improvements: - Modernization of the EP93xx driver to use irqdomain and other contemporary concepts. - The ingenic driver has been merged into the Ingenic pin control driver and removed from the GPIO subsystem. - Debounce support in the ftgpio010 driver" * tag 'gpio-v4.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (116 commits) gpio: Clarify kerneldoc on gpiochip_set_chained_irqchip() gpio: Remove unused 'irqchip' argument to gpiochip_set_cascaded_irqchip() gpio: Drop parent irq assignment during cascade setup mmc: pwrseq_simple: Fix incorrect handling of GPIO bitmap gpio: fix SNPS_CREG kconfig dependency warning gpiolib: Initialize gdev field before is used gpio: fix kernel-doc after devres.c file rename gpio: fix doc string for devm_gpiochip_add_data() to not talk about irq_chip gpio: syscon: Fix possible NULL ptr usage gpiolib: Show correct direction from the beginning pinctrl: msm: Use init_valid_mask exported function gpiolib: Add init_valid_mask exported function GPIO: add single-register GPIO via CREG driver dt-bindings: Document the Synopsys GPIO via CREG bindings gpio: mockup: use device properties instead of platform_data gpio: Slightly more helpful debugfs gpio: omap: Remove set but not used variable 'dev' gpio: omap: drop omap_gpio_list Accept partial 'gpio-line-names' property. gpio: omap: get rid of the conditional PM runtime calls ...
| * pinctrl: msm: Use init_valid_mask exported functionRicardo Ribalda Delgado2018-10-101-42/+37Star
| | | | | | | | | | | | | | | | | | | | The current code produces XPU violation if get_direction is called just after the initialization. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Acked-by: Timur Tabi <timur@kernel.org> Tested-by: Jeffrey Hugo <jhugo@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge tag 'pinctrl-v4.20-1' of ↵Linus Torvalds2018-10-23133-2530/+21539
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.20 series: There were no significant changes to the core this time! Bur the new Qualcomm, Mediatek and Broadcom drivers are quite interesting as they will be used in a few million embedded devices the coming years as it seems. New drivers: - Broadcom Northstar pin control driver. - Mediatek MT8183 subdriver. - Mediatek MT7623 subdriver. - Mediatek MT6765 subdriver. - Meson g12a subdriver. - Nuvoton NPCM7xx pin control and GPIO driver. - Qualcomm QCS404 pin control and GPIO subdriver. - Qualcomm SDM660 pin control and GPIO subdriver. - Renesas R8A7744 PFC subdriver. - Renesas R8A774C0 PFC subdriver. - Renesas RZ/N1 pinctrl driver Major improvements: - Pulled the GPIO support for Ingenic over from the GPIO subsystem and consolidated it all in the Ingenic pin control driver. - Major cleanups and consolidation work in all Intel drivers. - Major cleanups and consolidation work in all Mediatek drivers. - Lots of incremental improvements to the Renesas PFC pin controller family. - All drivers doing GPIO now include <linux/gpio/driver.h> and nothing else" * tag 'pinctrl-v4.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (153 commits) pinctrl: sunxi: Fix a memory leak in 'sunxi_pinctrl_build_state()' gpio: uniphier: include <linux/bits.h> instead of <linux/bitops.h> pinctrl: uniphier: include <linux/bits.h> instead of <linux/bitops.h> dt-bindings: pinctrl: bcm4708-pinmux: improve example binding pinctrl: geminilake: Sort register offsets by value pinctrl: geminilake: Get rid of unneeded ->probe() stub pinctrl: geminilake: Update pin list for B0 stepping pinctrl: renesas: Fix platform_no_drv_owner.cocci warnings pinctrl: mediatek: Make eint_m u16 pinctrl: bcm: ns: Use uintptr_t for casting data pinctrl: madera: Fix uninitialized variable bug in madera_mux_set_mux pinctrl: gemini: Fix up TVC clock group pinctrl: gemini: Drop noisy debug prints pinctrl: gemini: Mask and set properly pinctrl: mediatek: select GPIOLIB pinctrl: rza1: don't manually release devm managed resources MAINTAINERS: update entry for Mediatek pin controller pinctrl: bcm: add Northstar driver dt-bindings: pinctrl: document Broadcom Northstar pin mux controller pinctrl: qcom: fix 'const' pointer handling ...
| * | pinctrl: sunxi: Fix a memory leak in 'sunxi_pinctrl_build_state()'Christophe JAILLET2018-10-161-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If 'krealloc()' fails, 'pctl->functions' is set to NULL. We should instead use a temp variable in order to be able to free the previously allocated memeory, in case of OOM. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: uniphier: include <linux/bits.h> instead of <linux/bitops.h>Masahiro Yamada2018-10-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The reason of including <linux/bitops.h> here is just for BIT() macro. Since commit 8bd9cb51daac8 ("locking/atomics, asm-generic: Move some macros from <linux/bitops.h> to a new <linux/bits.h> file"), <linux/bits.h> is enough for such compile-time macros. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: geminilake: Sort register offsets by valueAndy Shevchenko2018-10-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | No functional change. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: geminilake: Get rid of unneeded ->probe() stubAndy Shevchenko2018-10-161-6/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The local ->probe() stub does nothing except calling a generic Intel pin control probe function. Thus, it's not needed and generic function may be called directly. This patch converts the driver accordingly. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: geminilake: Update pin list for B0 steppingAndy Shevchenko2018-10-161-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to an updated pin list few names of the pins can be spelled better, taking into account their primary functions. Thus, update a pin list to cover B0 stepping. Note, SPI numbering had been fixed even in A0 public documentation. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: renesas: Fix platform_no_drv_owner.cocci warningsYueHaibing2018-10-151-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: mediatek: Make eint_m u16Manivannan Sadhasivam2018-10-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For SoC's which lacks EINT support, U16_MAX is assigned to both eint_m and eint_n through macro NO_EINT_SUPPORT. This will generate integer overflow warning because eint_m is declared as u8 type. Hence modify the eint_m type to u16. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: bcm: ns: Use uintptr_t for casting dataRafał Miłecki2018-10-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fix up a compiler error on 64bit architectures where pointers and integers differ in size. Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: madera: Fix uninitialized variable bug in madera_mux_set_muxGustavo A. R. Silva2018-10-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a potential execution path in which variable *ret* is checked in an IF statement, and then its value is used to report an error at line 659 without being properly initialized previously: 659 if (ret) 660 dev_err(priv->dev, "Failed to write to 0x%x (%d)\n", reg, ret); Fix this by initializing variable *ret* to 0 in order to avoid unpredictable or unintended results. Addresses-Coverity-ID: 1471969 ("Uninitialized scalar variable") Fixes: 218d72a77b0b ("pinctrl: madera: Add driver for Cirrus Logic Madera codecs") Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: gemini: Fix up TVC clock groupLinus Walleij2018-10-101-8/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous fix made the TVC clock get muxed in on the D-Link DIR-685 instead of giving nagging warnings of this not working. Not good. We didn't want that, as it breaks video. Create a specific group for the TVC CLK, and break out a specific GPIO group for it on the SL3516 so we can use that line as GPIO if we don't need the TVC CLK. Fixes: d17f477c5bc6 ("pinctrl: gemini: Mask and set properly") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: gemini: Drop noisy debug printsLinus Walleij2018-10-101-16/+16
| | | | | | | | | | | | | | | | | | | | | The dev_info() in the pin control driver is really just good for debug, so drop it. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: gemini: Mask and set properlyLinus Walleij2018-10-101-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code was written under the assumption that the regmap_update_bits() would mask the bits in the mask and set the bits in the value. It missed the points that it will not set bits in the value unless these are also masked in the mask. Set value bits that are not in the mask will simply be ignored. Fixes: 06351d133dea ("pinctrl: add a Gemini SoC pin controller") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: mediatek: select GPIOLIBArnd Bergmann2018-10-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Removing the linux/gpio.h include means we no longer have a declaration of gpiochip_lock_as_irq() when CONFIG_GPIOLIB is disabled: drivers/pinctrl/mediatek/mtk-eint.c: In function 'mtk_eint_irq_request_resources': drivers/pinctrl/mediatek/mtk-eint.c:247:8: error: implicit declaration of function 'gpiochip_lock_as_irq'; did you mean 'spin_lock_irq'? [-Werror=implicit-function-declaration] drivers/pinctrl/mediatek/mtk-eint.c: In function 'mtk_eint_irq_release_resources': drivers/pinctrl/mediatek/mtk-eint.c:272:2: error: implicit declaration of function 'gpiochip_unlock_as_irq'; did you mean 'spin_unlock_irq'? [-Werror=implicit-function-declaration] Select it explictly instead. Fixes: 1c5fb66afa2a ("pinctrl: Include <linux/gpio/driver.h> nothing else") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: rza1: don't manually release devm managed resourcesUwe Kleine-König2018-10-101-7/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | If the probe function fails the driver core cares to return the allocated resources automatically. So the driver can be simplified accordingly. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | Merge tag 'sh-pfc-for-v4.20-tag3' of ↵Linus Walleij2018-10-104-2/+1021
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.20 (take three) - Add support for the new RZ/N1D (R9A06G032) and RZ/N1S (R9A06G033) SoCs, - Add INTC-EX pin groups on R-Car E3.
| | * | pinctrl: sh-pfc: r8a77990: Add INTC-EX pins, groups and functionGeert Uytterhoeven2018-10-021-2/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups, and function for the Interrupt Controller for External Devices (INTC-EX) on the R-Car E3 SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * | pinctrl: renesas: Renesas RZ/N1 pinctrl driverPhil Edworthy2018-10-023-0/+959
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This provides a pinctrl driver for the Renesas RZ/N1 device family. Based on a patch originally written by Michel Pollet at Renesas. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | pinctrl: bcm: add Northstar driverRafał Miłecki2018-10-103-0/+386
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver provides support for Northstar mux controller. It differs from Northstar Plus one so a new binding and driver were needed. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: qcom: fix 'const' pointer handlingArnd Bergmann2018-10-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'tiles' array is initialized to a constant pointers to constant strings, but the declaration is only half as constant: drivers/pinctrl/qcom/pinctrl-qcs404.c:1660:11: error: initialization discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers] drivers/pinctrl/qcom/pinctrl-sdm660.c:1417:11: error: initialization discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers] Let's make it more constant. Fixes: 22eb8301dbc1 ("pinctrl: qcom: Add qcs404 pinctrl driver") Fixes: a46d5e98190d ("pinctrl: qcom: Support dispersed tiles") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: nomadik: Fix debugfsLinus Walleij2018-10-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The .to_irq() function obviously takes the per-chip offset as parameter, not the global GPIO number. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: intel: Fix a spelling typo in kernel documentationAndy Shevchenko2018-10-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The parameter 'community' had been spelled incorrectly. Fix it here. As a side effect it satisfies static checkers that issue the following warnings: drivers/pinctrl/intel/pinctrl-intel.c:845: warning: Function parameter or member 'community' not described in 'intel_gpio_to_pin' drivers/pinctrl/intel/pinctrl-intel.c:845: warning: Excess function parameter 'commmunity' description in 'intel_gpio_to_pin' Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: broxton: Convert unsigned to unsigned intAndy Shevchenko2018-10-031-53/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simple type conversion with no functional change implied. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: cherryview: Convert unsigned to unsigned intAndy Shevchenko2018-10-031-33/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simple type conversion with no functional change implied. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: baytrail: Convert unsigned to unsigned intAndy Shevchenko2018-10-031-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simple type conversion with no functional change implied. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: intel: Convert unsigned to unsigned intAndy Shevchenko2018-10-032-66/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simple type conversion with no functional change implied. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: msm: Actually use function 0 for gpio selectionStephen Boyd2018-10-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code needs to select function #0, which is the first int in the array of functions, not the number 0 which may or may not be the function for "GPIO mode" per the enum mapping. We were getting lucky on SDM845, where this was tested, because the function 0 matched the enum value for "GPIO mode". On other platforms, e.g. MSM8996, the gpio enum value is the last one in the list so this code doesn't work and we see a warning at boot. Fix it by grabbing the first element out of the array of functions. Cc: Doug Anderson <dianders@chromium.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Niklas Cassel <niklas.cassel@linaro.org> Reported-by: Niklas Cassel <niklas.cassel@linaro.org> Fixes: 1de7ddb3a15c ("pinctrl: msm: Mux out gpio function with gpio_request()") Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: core: make sure strcmp() doesn't get a null parameterYanjiang Jin2018-10-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some drivers, for example, QCOM's qdf2xxx, set groups[gpio].name only when gpio is valid, and leave invalid gpio names as null. If we want to access the sys node "pinconf-groups", pinctrl_get_group_selector() -> get_group_name() may return a null pointer if group_selector is invalid, then the below Kernel panic would happen since strcmp() uses this null pointer to do comparison. Unable to handle kernel NULL pointer dereference at ss 00000000 el:Internal error: Oops: 9600000[ 143.080279] SMP CPU: 19 PID: 2493 Comm: read_all Tainted: G O .aarch64 #1 Hardware name: HXT Semiconductor HXT REP-2 System PC is at strcmp+0x18/0x154 LR is at pinctrl_get_group_selector+0x6c/0xe8 Process read_all (pid: 2493, stack limit = Call trace: Exception stack strcmp+0x18/0x154 pin_config_group_get+0x64/0xd8 pinconf_generic_dump_one+0xd8/0x1c0 pinconf_generic_dump_pins+0x94/0xc8 pinconf_groups_show+0xb4/0x104 seq_read+0x178/0x464 full_proxy_read+0x6c/0xac __vfs_read+0x58/0x178 vfs_read+0x94/0x164 SyS_read+0x60/0xc0 __sys_trace_return+0x0/0x4 --[ end trace]-- Kernel panic - not syncing: Fatal exception Signed-off-by: Yanjiang Jin <yanjiang.jin@hxt-semitech.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | Merge tag 'sh-pfc-for-v4.20-tag2' of ↵Linus Walleij2018-10-0136-310/+1291
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.20 (take two) - Add MSIOF pin groups on R-Car E3 and D3, - Add support for the new RZ/G1N (R8A7744) and RZ/G2E (R8A774C0) SoCs, - Add I2C4, DU0, QSPI0, SDHI2, and USB pin groups on RZ/G1C, - Convert to SPDX license identifiers, - Small cleanups.
| | * | pinctrl: sh-pfc: rcar: Rename automotive-only arrays to automotiveGeert Uytterhoeven2018-09-283-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Renesas RZ/G SoCs are pin compatible with R-Car SoCs, but lack several automotive-specific peripherals. Currently pin groups and functions for automotive-specific peripherals are grouped in arrays named after the automative SoC part numbers. Rename them to "automotive" for clarity and consistency. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * | pinctrl: sh-pfc: r8a77470: Add USB pin groupsFabrizio Castro2018-09-201-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add USB[01] pin groups and functions to the R8A77470 SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groupsFabrizio Castro2018-09-201-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SDHI2 pin groups and functions to the R8A77470 SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a77470: Add QSPI0 pin groupsFabrizio Castro2018-09-201-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add QSPI0 pin groups and function to the R8A77470 SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a77470: Add DU0 pin groupsFabrizio Castro2018-09-201-0/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DU0 pin groups and function to the R8A77470 SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a77470: Add I2C4 pin groupsFabrizio Castro2018-09-201-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add I2C4 pin groups and function to the R8A77470 SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a77990: Add R8A774C0 PFC supportFabrizio Castro2018-09-195-151/+201
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Renesas RZ/G2E (a.k.a. r8a774c0) is pin compatible with R-Car E3 (a.k.a. r8a77990), however it doesn't have several automotive specific peripherals. Add a r8a77990 specific pin groups/functions along with common pin groups/functions for supporting both r8a77990 and r8a774c0 SoCs. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a7791: Add r8a7744 supportBiju Das2018-09-195-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Renesas RZ/G1N (R8A7744) is pin compatible with R-Car M2-W/N (R8A7791/3) and RZ/G1M. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: rza1: Convert to SPDX identifiersKuninori Morimoto2018-09-111-4/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates license to use SPDX-License-Identifier instead of verbose license text. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: Convert to SPDX identifiersKuninori Morimoto2018-09-1132-180/+34Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates license to use SPDX-License-Identifier instead of verbose license text. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a77995: Add MSIOF pins, groups and functionsTakeshi Kihara2018-09-111-0/+365
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds MSIOF{0,1,2,3} pins, groups and functions to R8A77995 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [ykaneko0929@gmail.com: fix the order of definitions] Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a77990: Add MSIOF pins, groups and functionsTakeshi Kihara2018-09-111-0/+405
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds MSIOF{0,1,2,3} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | Merge tag 'v4.19-rc6' into develLinus Walleij2018-10-016-107/+134
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the 4.19-rc6 release I needed to merge this in because of extensive conflicts in the MSM and Intel pin control drivers. I know how to resolve them, so let's do it like this. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: sprd: Move DT parsing before registering pinctrl deviceBaolin Wang2018-09-281-7/+6Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be failed to select default or sleep state for pins hogged by the pin controller device, since we hadn't parsed pins configuration in device tree before registering the pin controller device. Thus we should move the device tree parsing function before registering the pin controller device. Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: mediatek: mark dummy helpers as 'static inline'Arnd Bergmann2018-09-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mtk_eint_set_debounce and mtk_eint_find_irq are defined as stub functions in a header file, but without marking them as 'static inline', we get a copy for each file that includes the header: drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.o: In function `mtk_eint_set_debounce': pinctrl-mtk-common-v2.c:(.text+0x134): multiple definition of `mtk_eint_set_debounce' drivers/pinctrl/mediatek/pinctrl-moore.o:pinctrl-moore.c:(.text+0x7d0): first defined here drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.o: In function `mtk_eint_find_irq': pinctrl-mtk-common-v2.c:(.text+0x13c): multiple definition of `mtk_eint_find_irq' Fixes: e46df235b4e6 ("pinctrl: mediatek: refactor EINT related code for all MediaTek pinctrl can fit") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: mediatek: fix check on EINT_NA comparisonColin Ian King2018-09-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the check on desc->eint.eint_n == EINT_NA is always false because this is comparing a u16 to -1 which can never be true. Fix this by casting EINT_NA to u16. Detected by CoverityScan, CID#1473610 ("Operands don't affect result") Fixes: fb5fa8dc151b ("pinctrl: mediatek: extend struct mtk_pin_desc to pinctrl-mtk-common-v2.c") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: qcom: Add qcs404 pinctrl driverAvaneesh Kumar Dwivedi2018-09-263-0/+1706
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial pinctrl driver to support pin configuration with pinctrl framework for qcs404. Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org> Signed-off-by: Chintan Pandya <cpandya@codeaurora.org> Signed-off-by: Anu Ramanathan <anur@codeaurora.org> [bjorn: Reworked tile handling and did some minor rework] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: qcom: Support dispersed tilesBjorn Andersson2018-09-262-9/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some new platforms the tiles have been placed too far apart to be covered in a single ioremap. Turn "regs" into an array of base addresses and make the pingroup carry the information about which tile the pin resides in. For existing platforms we map the first entry regs and the existing pingroups will all use tile 0, meaning that there's no functional change. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: qcom: Introduce readl/writel accessorsBjorn Andersson2018-09-261-36/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for the support for dispersed tiles move all readl and writel calls to helper functions. This will allow us to isolate the added complexity of another indirection. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-11-14 07:37:08 +0100