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* pinctrl: aspeed: Make aspeed_pinmux_ips staticYueHaibing2019-07-291-1/+1
| | | | | | | | | | | | | Fix sparse warning: drivers/pinctrl/aspeed/pinmux-aspeed.c:8:12: warning: symbol 'aspeed_pinmux_ips' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20190711142457.37028-1-yuehaibing@huawei.com Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: aspeed-g5: Delay acquisition of regmapsAndrew Jeffery2019-07-294-37/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While sorting out some devicetree issues I found that the pinctrl driver was failing to acquire its GFX regmap even though the phandle was present in the devicetree: [ 0.124190] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: No GFX phandle found, some mux configurations may fail Without access to the GFX regmap we fail to configure the mux for the VPO function: [ 1.548866] pinctrl core: add 1 pinctrl maps [ 1.549826] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: found group selector 164 for VPO [ 1.550638] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 144 (V20) for 1e6e6000.display [ 1.551346] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 145 (U19) for 1e6e6000.display ... [ 1.562057] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 218 (T22) for 1e6e6000.display [ 1.562541] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 219 (R20) for 1e6e6000.display [ 1.563113] Muxing pin 144 for VPO [ 1.563456] Want SCU8C[0x00000001]=0x1, got 0x0 from 0x00000000 [ 1.564624] aspeed_gfx 1e6e6000.display: Error applying setting, reverse things back This turned out to be a simple problem of timing: The ASPEED pinctrl driver is probed during arch_initcall(), while GFX is processed much later. As such the GFX syscon is not yet registered during the pinctrl probe() and we get an -EPROBE_DEFER when we try to look it up, however we must not defer probing the pinctrl driver for the inability to mux some GFX-related functions. Switch to lazily grabbing the regmaps when they're first required by the mux configuration. This generates a bit of noise in the patch as we have to drop the `const` qualifier on arguments for several function prototypes, but has the benefit of working. I've smoke tested this for the ast2500-evb under qemu with a dummy graphics device. We now succeed in our attempts to configure the SoC's VPO pinmux function. Fixes: 7d29ed88acbb ("pinctrl: aspeed: Read and write bits in LPC and GFX controllers") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190724080155.12209-1-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v5.3-1' of ↵Linus Torvalds2019-07-1473-2739/+6056
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.3 kernel cycle: Core changes: - Device links can optionally be added between a pin control producer and its consumers. This will affect how the system power management is handled: a pin controller will not suspend before all of its consumers have been suspended. This was necessary for the ST Microelectronics STMFX expander and need to be tested on other systems as well: it makes sense to make this default in the long run. Right now it is opt-in per driver. - Drive strength can be specified in microamps. With decreases in silicon technology, milliamps isn't granular enough, let's make it possible to select drive strengths in microamps. Right now the Meson (AMlogic) driver needs this. New drivers: - New subdriver for the Tegra 194 SoC. - New subdriver for the Qualcomm SDM845. - New subdriver for the Qualcomm SM8150. - New subdriver for the Freescale i.MX8MN (Freescale is now a product line of NXP). - New subdriver for Marvell MV98DX1135. Driver improvements: - The Bitmain BM1880 driver now supports pin config in addition to muxing. - The Qualcomm drivers can now reserve some GPIOs as taken aside and not usable for users. This is used in ACPI systems to take out some GPIO lines used by the BIOS so that noone else (neither kernel nor userspace) will play with them by mistake and crash the machine. - A slew of refurbishing around the Aspeed drivers (board management controllers for servers) in preparation for the new Aspeed AST2600 SoC. - A slew of improvements over the SH PFC drivers as usual. - Misc cleanups and fixes" * tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (106 commits) pinctrl: aspeed: Strip moved macros and structs from private header pinctrl: aspeed: Fix missed include pinctrl: baytrail: Use GENMASK() consistently pinctrl: baytrail: Re-use data structures from pinctrl-intel.h pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux() pinctrl: qcom: Add SM8150 pinctrl driver dt-bindings: pinctrl: qcom: Add SM8150 pinctrl binding dt-bindings: pinctrl: qcom: Document missing gpio nodes pinctrl: aspeed: Add implementation-related documentation pinctrl: aspeed: Split out pinmux from general pinctrl pinctrl: aspeed: Clarify comment about strapping W1C pinctrl: aspeed: Correct comment that is no longer true MAINTAINERS: Add entry for ASPEED pinctrl drivers dt-bindings: pinctrl: aspeed: Convert AST2500 bindings to json-schema dt-bindings: pinctrl: aspeed: Convert AST2400 bindings to json-schema dt-bindings: pinctrl: aspeed: Split bindings document in two pinctrl: qcom: Add irq_enable callback for msm gpio pinctrl: madera: Fixup SPDX headers pinctrl: qcom: sdm845: Fix CONFIG preprocessor guard pinctrl: tegra: Add bitmask support for parked bits ...
| * pinctrl: aspeed: Strip moved macros and structs from private headerAndrew Jeffery2019-07-101-498/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | Further cleanup from the SPDX fixup fallout for the recent ASPEED series. aspeed_g4_defconfig, aspeed_g5_defconfig and multi_v5_defconfig now compile. Smoke tested the g4 and g5 kernels under QEMU's palmetto-bmc and romulus-bmc machines respectively. Fixes: 35d8510ea3ad ("pinctrl: aspeed: Fix missed include") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190710032216.4088-1-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: aspeed: Fix missed includeLinus Walleij2019-07-101-0/+2
| | | | | | | | | | | | | | | | | | Some SPDX churn made my fixes drop an important include from the Aspeed pinctrl header. Fix it up. Cc: Andrew Jeffery <andrew@aj.id.au> Reported-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: baytrail: Use GENMASK() consistentlyAndy Shevchenko2019-07-041-9/+7Star
| | | | | | | | | | | | | | | | | | | | Use GENMASK() macro for all definitions where it's appropriate. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20190703151554.30454-1-andriy.shevchenko@linux.intel.com Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: baytrail: Re-use data structures from pinctrl-intel.hAndy Shevchenko2019-07-041-239/+60Star
| | | | | | | | | | | | | | | | | | | | | | We have some data structures duplicated across the drivers. Let's deduplicate them by using ones that being provided by pinctrl-intel.h. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20190703003018.75186-2-andriy.shevchenko@linux.intel.com Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux()Andy Shevchenko2019-07-041-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | By the fact byt_get_gpio_mux() returns a value of mux settings as it is represented in hardware. Use defined macro instead of magic numbers to clarify this. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20190703003018.75186-1-andriy.shevchenko@linux.intel.com Reviewed-By: Enrico Weigelt <info@metux.net> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: Add SM8150 pinctrl driverPrasad Sodagudi2019-07-043-0/+1558
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial pinctrl driver to support pin configuration with pinctrl framework for SM8150 Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org> Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org> [vkoul: modify to use upstream tile support use upstream code style order the functions and squash functions] Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20190702105045.27646-4-vkoul@kernel.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: aspeed: Add implementation-related documentationAndrew Jeffery2019-07-031-4/+200
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ASPEED pinctrl driver implementations make heavy use of macros to minimise tedium of implementation and maximise the chance that the compiler will catch errors in defining signal and pin configurations. While the goal of minimising errors is achieved, it is at the cost of the complexity of the macros. Document examples of the expanded form of pin declarations to demonstrate the operation of the macros. Cc: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190628023838.15426-9-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: aspeed: Split out pinmux from general pinctrlAndrew Jeffery2019-07-037-255/+888
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ASPEED have completely rearranged the System Control Unit register layout with the AST2600. The existing code took advantage of the fact that the AST2400 and AST2500 had layouts that were similar enough to have little impact on the pinmux infrastructure (though there is a wart with read-modify-write vs write-1-clear semantics of the hardware strapping registers between the two). Given that any similarity has been thrown out with the AST2600, separate out the function applying an expression state to be driver-specific. With it, extract out the pinmux macro jungle to its own header and implementation so the pieces can be composed without dependency cycles. Cc: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190628023838.15426-8-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: aspeed: Clarify comment about strapping W1CAndrew Jeffery2019-07-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Writes of 1 to SCU7C clear set bits in SCU70, the hardware strapping register. The information was correct if you squinted while reading, but hopefully switching the order of the registers as listed conveys it better. Cc: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20190628023838.15426-7-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: aspeed: Correct comment that is no longer trueAndrew Jeffery2019-07-031-2/+1Star
| | | | | | | | | | | | | | | | | | | | We have handled the GFX register case for quite some time now. Cc: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20190628023838.15426-6-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: Add irq_enable callback for msm gpioSrinivas Ramana2019-07-031-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce the irq_enable callback which will be same as irq_unmask except that it will also clear the status bit before unmask. This will help in clearing any erroneous interrupts that would have got latched when the interrupt is not in use. There may be devices like UART which can use the same gpio line for data rx as well as a wakeup gpio when in suspend. The data that was flowing on the line may latch the interrupt and when we enable the interrupt before going to suspend, this would trigger the unexpected interrupt. This change helps clearing the interrupt so that these unexpected interrupts gets cleared. Signed-off-by: Srinivas Ramana <sramana@codeaurora.org> Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org> Link: https://lore.kernel.org/r/1561472086-23360-1-git-send-email-neeraju@codeaurora.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: madera: Fixup SPDX headersCharles Keepax2019-06-265-25/+5Star
| | | | | | | | | | | | | | | | | | GPL-2.0-only is the preferred way of expressing v2 of the GPL, so switch to that. Remove some redundant copyright notices and correct some instances where the wrong comment type has been used in header files. Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: sdm845: Fix CONFIG preprocessor guardNathan Chancellor2019-06-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clang warns when CONFIG_ACPI is unset: drivers/pinctrl/qcom/pinctrl-sdm845.c:1320:5: warning: 'CONFIG_ACPI' is not defined, evaluates to 0 [-Wundef] #if CONFIG_ACPI ^ 1 warning generated. Use ifdef instead of if to resolve this. Fixes: a229105d7a1e ("pinctrl: qcom: sdm845: Provide ACPI support") Link: https://github.com/ClangBuiltLinux/linux/issues/569 Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: tegra: Add bitmask support for parked bitsThierry Reding2019-06-258-47/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some pin groups have park bits for multiple pins in one register. Support this by turning the parked bit field into a parked bitmask field. If no parked bits are supported, the bitmask can be 0. Update the pingroup table on Tegra210, which is the only generation where this is supported, with the parked bitmask. Signed-off-by: Thierry Reding <treding@nvidia.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: tegra: Set specific GPIO compatible stringThierry Reding2019-06-253-3/+3
| | | | | | | | | | | | | | | | | | | | | | Rather than reuse the nvidia,tegra30-gpio compatible string to find the GPIO controller on Tegra30, Tegra114, Tegra124 and Tegra210, use the most specific compatible string for each SoC generation for consistency. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mvebu: Add support for MV98DX1135Chris Packham2019-06-251-279/+297
| | | | | | | | | | | | | | | | | | The 98DX1135 is a switch chip with an integrated CPU. This is similar to the 98DX4122 except the MPP assignments differ. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: freescale: Add i.MX8MN pinctrl driver supportAnson Huang2019-06-253-0/+356
| | | | | | | | | | | | | | | | Add the pinctrl driver support for i.MX8MN. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: Minimize SPDX hamming distanceLinus Walleij2019-06-203-3/+2Star
| | | | | | | | | | | | | | | | | | | | | | OK so some automatic scripts were fixing the SPDX tags in the mainline branch while we were patching other stuff, and yeah it is more correct to have "GPL-2.0-only" rather than "GPL-2.0" so let's conform to what is already upstream so we don't end up getting the wrong license on the merged result later. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * Merge branch 'ib-qcom-acpi' into develLinus Walleij2019-06-124-2/+55
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| | * pinctrl: qcom: sdm845: Provide ACPI supportLee Jones2019-06-122-2/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides basic support for booting with ACPI instead of the currently supported Device Tree. When doing so there are a couple of differences which we need to taken into consideration. Firstly, the SDM850 ACPI tables omit information pertaining to the 4 reserved GPIOs on the platform. If Linux attempts to touch/ initialise any of these lines, the firmware will restart the platform. Secondly, when booting with ACPI, it is expected that the firmware will set-up things like; Regulators, Clocks, Pin Functions, etc in their ideal configuration. Thus, the possible Pin Functions available to this platform are not advertised when providing the higher GPIOD/Pinctrl APIs with pin information. Signed-off-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| | * pinctrl: msm: Add ability for drivers to supply a reserved GPIO listLee Jones2019-06-122-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting MSM based platforms with Device Tree or some ACPI implementations, it is possible to provide a list of reserved pins via the 'gpio-reserved-ranges' and 'gpios' properties respectively. However some ACPI tables are not populated with this information, thus it has to come from a knowledgable device driver instead. Here we provide the MSM common driver with additional support to parse this informtion and correctly populate the widely used 'valid_mask'. Signed-off-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: remove unused pin_is_valid()Masahiro Yamada2019-06-121-23/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function was used by pin_request() to pointlessly double-check the pin validity, and it was the only user ever. Since commit d2f6a1c6fb0e ("pinctrl: remove double pin validity check."), no one has ever used it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: remove unneeded initializer for list_for_each_entry() iteratorMasahiro Yamada2019-06-121-4/+4
| | | | | | | | | | | | | | | | | | | | | The iterator is initialized in list_for_each_entry(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | Merge tag 'sh-pfc-for-v5.3-tag1' of ↵Linus Walleij2019-06-0823-1059/+1245
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v5.3 - Add more checks for pinctrl table validation, - Add TPU (Timer Pulse Unit / PWM) pin groups on R-Car H3, M3-W, and M3-N, - Rework description of pins without GPIO functionality, - Small fixes and cleanups.
| | * | pinctrl: sh-pfc: Remove obsolete SH_PFC_PIN_NAMED*() macrosGeert Uytterhoeven2019-06-041-16/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now all Renesas pin control drivers have been converted to use the new non-GPIO helper macros, SH_PFC_PIN_NAMED() and SH_PFC_PIN_NAMED_CFG() are no longer used. Remove them. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| | * | pinctrl: sh-pfc: sh73a0: Use new macros for non-GPIO pinsGeert Uytterhoeven2019-06-041-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the SH-Mobile AG5 pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the SH-Mobile AG5 SoC (in 34x34 BGA package) by symbolic enum values, referring to signal names. Note that the user-visible names of these pins are still based on pin numbers instead of signal names, to preserve DT backwards compatibility. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| | * | pinctrl: sh-pfc: r8a77990: Use new macros for non-GPIO pinsGeert Uytterhoeven2019-06-041-46/+41Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the R-Car E3 pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car E3 SoC (in 25x25 FCBGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| | * | pinctrl: sh-pfc: r8a77965: Use new macros for non-GPIO pinsGeert Uytterhoeven2019-06-041-156/+151Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the R-Car M3-N pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car M3-N SiP (in 39x39 BGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| | * | pinctrl: sh-pfc: r8a7796: Use new macros for non-GPIO pinsGeert Uytterhoeven2019-06-041-156/+151Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the R-Car M3-W pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car M3-W SiP (in 39x39 BGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| | * | pinctrl: sh-pfc: r8a7795: Use new macros for non-GPIO pinsGeert Uytterhoeven2019-06-041-159/+154Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the R-Car H3 ES2.0 and later pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car H3 ES2.0 SiP (in 39x39 BGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| | * | pinctrl: sh-pfc: r8a7795-es1: Use new macros for non-GPIO pinsGeert Uytterhoeven2019-06-041-170/+163Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the R-Car H3 ES1.x pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car H3 ES1.x SiP (in 39x39 BGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| | * | pinctrl: sh-pfc: r8a7790: Use new macros for non-GPIO pinsGeert Uytterhoeven2019-06-041-15/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the R-Car H2 pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car H2 SoC (in 31x31 FCBGA package) by symbolic enum values, referring to signal names. Note that the user-visible names of these pins are still based on pin numbers instead of signal names, to preserve DT backwards compatibility. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| | * | pinctrl: sh-pfc: r8a7778: Use new macros for non-GPIO pinsGeert Uytterhoeven2019-06-041-13/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the R-Car M1A pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car M1A SoC (in 25x25 FCBGA package) by symbolic enum values, referring to signal names. Note that the user-visible names of these pins are still based on pin numbers instead of signal names, to preserve DT backwards compatibility. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| | * | pinctrl: sh-pfc: emev2: Use new macros for non-GPIO pinsGeert Uytterhoeven2019-06-041-36/+34Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the EMMA Mobile EV2 pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the EMMA Mobile EV2 SoC (in 23x23 BGA package) by symbolic enum values, referring to signal names. Note that the user-visible names of these pins are still based on pin numbers instead of signal names, to preserve DT backwards compatibility. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| | * | pinctrl: sh-pfc: Add new non-GPIO helper macrosGeert Uytterhoeven2019-06-041-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new macros for describing pins without GPIO functionality: - NOGP_ALL() expands to a list of PIN_id values, to be used for generating symbolic enum values, - PINMUX_NOGP_ALL() expands to a list of sh_pfc_pin entries, to list all pins and their capabilities. Both macros depend on an SoC-specific CPU_ALL_NOGP() macro, to be provided by each individual SoC pin control driver. The new macros offer two advantages over the existing SH_PFC_PIN_NAMED() and SH_PFC_PIN_NAMED_CFG() macros: 1. They do not rely on PIN_NUMBER() macros and physical pin numbering, hence do not suffer from pin numbering confusion among different SoC/SiP packages. 2. They are similar in spirit to the existing scheme for handling pins with GPIO functionality. Note that internal to the driver, non-GPIO pins use a sequential numbering scheme which starts after the highest GPIO pin number in use. This value is calculated automatically, using two new helper macros, for systems with either 32-port bank (GP port style) or linear (PORT style) pin space. Sample expansion: GP_LAST = sizeof(union { char dummy[0] __attribute__((deprecated, deprecated)); char GP_0_0[(0 * 32) + 0] __attribute__((deprecated, deprecated)); char GP_0_1[(0 * 32) + 1] __attribute__((deprecated, deprecated)); ... char GP_7_3[(7 * 32) + 3] __attribute__((deprecated, deprecated)); }) Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| | * | pinctrl: sh-pfc: r8a7778: Use common PORT_GP_CFG_27() macroGeert Uytterhoeven2019-05-211-17/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Get rid of the custom PORT_GP_PUP_27() macro by using the common PORT_GP_CFG_27() macro instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * | pinctrl: sh-pfc: Add PORT_GP_27 helper macroGeert Uytterhoeven2019-05-211-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This follows the style of the existing PORT_GP_X macros, and will be used by a follow-up patch for the r8a7778 SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * | pinctrl: sh-pfc: r8a77965: Add TPU pins, groups and functionsGeert Uytterhoeven2019-05-211-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs on the R-Car M3-N SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * | pinctrl: sh-pfc: r8a7796: Add TPU pins, groups and functionsGeert Uytterhoeven2019-05-211-2/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs on the R-Car M3-W and RZ/G2M SoCs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * | pinctrl: sh-pfc: r8a7795: Add TPU pins, groups and functionsGeert Uytterhoeven2019-05-211-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs on revisions ES2.x and later of the R-Car H3 SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * | pinctrl: sh-pfc: r8a7795-es1: Add TPU pins, groups and functionsGeert Uytterhoeven2019-05-211-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs on revision ES1.x of the R-Car H3 SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * | pinctrl: sh-pfc: r8a77970: Remove MMC_{CD,WP}Geert Uytterhoeven2019-05-211-22/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hardware Manual Errata for rev. 1.50 of March 26, 2019 removed the bit definitions for MMC_CD and MMC_WP in the documentation for the IPSR6 and IPSR7 registers, as these pin functionalities do not exist on R-Car V3M. Remove the definitions, and the corrresponding pins and groups. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
| | * | pinctrl: sh-pfc: Move PIN_NONE to shared header fileGeert Uytterhoeven2019-05-217-194/+189Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several drivers have identical definitions for PIN_NONE. Provide a definition with a SH_PFC_ prefix for general use in sh_pfc.h, and convert all drivers over to use it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * | pinctrl: sh-pfc: Add SH_PFC_PIN_CFG_PULL_UP_DOWN shorthandGeert Uytterhoeven2019-05-2110-35/+27Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is very common for a pin to support both pull-up and pull-down functionality. Hence add a shorthand SH_PFC_PIN_CFG_PULL_UP_DOWN. This not only reduces typing, but also avoids the need for several line breaks, and makes many overly long lines shorter, improving readability. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * | pinctrl: sh-pfc: Rename 2-parameter CPU_ALL_PORT() variantGeert Uytterhoeven2019-05-2117-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two variants of the CPU_ALL_PORT() macro in use: 1. A three-parameter variant, to be provided for SoCs with a linear GPIO pin space ("PORT style"), 2. A two-parameter variant, to be provided for SoCs with 32-port GPIO banks ("GP port style"). Rename the 2-parameter variant to CPU_ALL_GP(), to avoid confusion, and to increase naming consistency. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * | pinctrl: sh-pfc: Validate pin tables at runtimeGeert Uytterhoeven2019-05-211-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend the run-time debug code with checks to ensure there are no conflicting pin names, numbers, or enumeration values. This helps catching bugs early. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| | * | pinctrl: sh-pfc: Add check for empty pinmux groups/functionsGeert Uytterhoeven2019-05-211-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pinmux groups and functions arrays may contain two parts, to ease supporting SoCs that expose pin subsets of other related SoCs. Both parts need to be declared with explicit sizes, which thus need to be updated when adding support for more groups and functions. If a size is too small, the compiler will detect this at build time ("excess elements in array initializer"). If a size is too large, this may go undetected (for pin groups), lead to pin controller registration failures (for pin functions: "pinmux ops has no name for functionN"), or crash the optional run-time debug code (for pin groups). Extend the run-time debug code with checks to detect this, to help catching bugs early. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
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