summaryrefslogtreecommitdiffstats
path: root/drivers/pinctrl
Commit message (Collapse)AuthorAgeFilesLines
...
| | * | pinctrl: sh-pfc: r8a7795: Fix trivial typo in commentWolfram Sang2017-10-111-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a7795: Add HSCIF pins, groups, and functionsWolfram Sang2017-10-111-0/+283
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a7796: Add support for INTC-EX IRQ pinsTakeshi Kihara2017-10-111-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most pins on the r8a7796 SoC can be configured in GPIO mode for interrupt and GPIO functionality, while a couple of them can also be routed to the INTC-EX hardware block (formerly known as IRQC). On r8a7795 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and this patch adds support for them to the PFC driver as "intc_ex_irqN". [takeshi.kihara.df: Ported from commit bb46f6f3f3bf ("pinctrl: sh-pfc: r8a7795: Add support for INTC-EX IRQ pins") to drivers/pinctrl/sh-pfc/pfc-r8a7796.c] Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a7795: Add INTC-EX pins, groups and functionGeert Uytterhoeven2017-10-111-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups, and a function for the INTC-EX interrupt controller on R-Car H3 ES2.0. Extracted from a big patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: rza1: Add support for RZ/A1LChris Brandt2017-10-091-0/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Aspects like the number of ports and the location where peripherals are brought out differ between the RZ/A1H and RZ/A1L. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a7795: Restore sort orderGeert Uytterhoeven2017-10-051-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | Move the SCIF_CLK pins where they belong. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a7795-es1: Restore sort orderGeert Uytterhoeven2017-10-051-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | Move the USB30 pins where they belong. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a7795: Add I2C pin supportWolfram Sang2017-10-041-0/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since pinmuxing for I2C is equal on H3 ES1.0 and later versions, copy the I2C settings from ES1.0. Fixes this error in upstream for Salvator-XS: sh-pfc e6060000.pin-controller: function 'i2c2' not supported sh-pfc e6060000.pin-controller: invalid function i2c2 in map table i2c-rcar: probe of e6510000.i2c failed with error -22 Now, the bus works the same as with other Salvator boards. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a77995: Add PWM pins, groups and functionsTakeshi Kihara2017-10-041-0/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for PWM on r8a77995. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a7795: Add Audio SSI pin supportKuninori Morimoto2017-10-041-0/+231
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a7795: Add Audio clock pin supportKuninori Morimoto2017-10-041-0/+159
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | gpio: mcp23s08: add support for mcp23018Phil Reid2017-10-191-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the required definitions for the mcp23018 which is the i2c variant of the mcp23s18. Signed-off-by: Phil Reid <preid@electromag.com.au> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: adi2: Fix Kconfig build problemLinus Walleij2017-10-191-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The build robot is complaining on Blackfin: drivers/pinctrl/pinctrl-adi2.c: In function 'port_setup': >> drivers/pinctrl/pinctrl-adi2.c:221:21: error: dereferencing pointer to incomplete type 'struct gpio_port_t' writew(readw(&regs->port_fer) & ~BIT(offset), ^~ drivers/pinctrl/pinctrl-adi2.c: In function 'adi_gpio_ack_irq': >> drivers/pinctrl/pinctrl-adi2.c:266:18: error: dereferencing pointer to incomplete type 'struct bfin_pint_regs' if (readl(&regs->invert_set) & pintbit) ^~ It seems the driver need to include <asm/gpio.h> and <asm/irq.h> to compile. The Blackfin architecture was re-defining the Kconfig PINCTRL symbol which is not OK, so replaced this with PINCTRL_BLACKFIN_ADI2 which selects PINCTRL and PINCTRL_ADI2 just like most arches do. Further, the old GPIO driver symbol GPIO_ADI was possible to select at the same time as selecting PINCTRL. This was not working because the arch-local <asm/gpio.h> header contains an explicit #ifndef PINCTRL clause making compilation break if you combine them. The same is true for DEBUG_MMRS. Make sure the ADI2 pinctrl driver is not selected at the same time as the old GPIO implementation. (This should be converted to use gpiolib or pincontrol and move to drivers/...) Also make sure the old GPIO_ADI driver or DEBUG_MMRS is not selected at the same time as the new PINCTRL implementation, and only make PINCTRL_ADI2 selectable for the Blackfin families that actually have it. This way it is still possible to add e.g. I2C-based pin control expanders on the Blackfin. Cc: Steven Miao <realmz6@gmail.com> Cc: Huanhuan Feng <huanhuan.feng@analog.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: meson: rework pinmux opsJerome Brunet2017-10-1610-109/+194
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change prepare the introduction of new meson SoC. This new SoC will share the same gpio/pinconf registers but the pinmux part will be different. While the format of the data associated with each pinmux group will change, the way to handle pinmuxing will be similar. To deal with this new situation, the meson_pmx_struture is kept but the data associated to it is now generic. This allows to reuse the basic functions which would otherwise be copy/pasted in each pinmux driver (such as getting the name a count of groups and functions) Only the functions actually using this specific data is taken out of the common code and is handling the SoC pinmuxing Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: meson: separate soc driversJerome Brunet2017-10-169-79/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When meson pinctrl is enabled, all meson platforms pinctrl drivers are built in the kernel, with a significant amount of data. This leads to situation where pinctrl drivers targeting an architecture are also compiled and shipped on another one (ex: meson8 - ARM - compiled and shipped on ARM64 builds). This is a waste of memory we can easily avoid. This change makes 4 pinctrl drivers (1 per SoC) out the original single driver, allowing to compile and ship only the ones required. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: gemini: Add missing functionsLinus Walleij2017-10-141-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some two functions were missing from the Gemini pin control driver. Noticed when trying to use ethernet. Fix it up by adding them. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: Do not depend in GPIOLIB, select itLinus Walleij2017-10-122-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of depends on GPIOLIB and having to run around in Kconfig menus looking for why your device is not available, simply select it from the pin control drivers that need it. The Kconfig for GPIOLIB is improved, selectable and this should "just work". Cc: Phil Reid <preid@electromag.com.au> Cc: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Cc: Peter Rosin <peda@axentia.se> Cc: Andrey Smirnov <andrew.smirnov@gmail.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: qcom: spmi-gpio: Update GPIO EN_CTL when setting pin configFenglin Wu2017-10-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO is expected to be disabled iff PIN_CONFIG_BIAS_HIGH_IMPEDANCE is configured. Update is_enabled flag in config_set() so that it can reflect GPIO status correctly. Also modify EN_CTL register based on is_enabled flag in config_set() to configure the GPIO properly. Signed-off-by: Fenglin Wu <fenglinw@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: mcp23s08: remove unused variables from pinconf_setPhil Reid2017-10-111-4/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Variable mask and val are not used in the mcp_pinconf_set(). Signed-off-by: Phil Reid <preid@electromag.com.au> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: change Kconfig PINCTRL variable to a menuconfigPhil Reid2017-10-111-5/+4Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows PINCTRL to be selected manually to allow enabling of the mcp23s08 i2c/spi gpio driver. Which is not platform specific. Signed-off-by: Phil Reid <preid@electromag.com.au> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: meson: remove unused pin_baseJerome Brunet2017-10-111-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While removing the need to have pin_base defined in meson pinctrl drivers, I forgot to remove the corresponding field from the pinctrl_data structure. Fixing this now. Fixes: 70e5ecb1b994 ("pinctrl: meson: get rid of pin_base") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: meson-gx: add TEST_N i2s pinmuxJerome Brunet2017-10-112-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add TEST_N pinmux for channel 6 and 7 of the i2s output Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: sx150x: make struct sx150x_regmap_config staticColin Ian King2017-10-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The structure sx150x_regmap_config is local to the source and does not need to be in global scope, so make it static. Cleans up sparse warning: symbol 'sx150x_regmap_config' was not declared. Should it be static? Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: ingenic: make function ingenic_pinctrl_probe staticColin Ian King2017-10-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function ingenic_pinctrl_probe is local to the source and does not need to be in global scope, so make it static. Cleans up sparse warnings symbol 'ingenic_pinctrl_probe' was not declared. Should it be static? Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | Merge tag 'sh-pfc-for-v4.15-tag1' of ↵Linus Walleij2017-10-073-0/+744
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.15 - Add SDHI and DRIF pin groups on R-Car H3 ES2.0, - Add USB3.0 host pin groups on R-Car H3 (ES1.x and ES2.0), - Add EthernetAVB and USB2.0 host pin groups on R-Car D3.
| | * | pinctrl: sh-pfc: r8a7795: Add USB3.0 host supportTakeshi Kihara2017-10-021-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds USB3.0 ch0 pinmux support to R8A7795 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a7795-es1: Add USB3.0 host supportTakeshi Kihara2017-10-021-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds USB3{0,1} (USB3.0 host) pinmux support to R8A7795 ES1.x SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a77995: Add USB2.0 host supportTakeshi Kihara2017-09-191-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a77995: Add EthernetAVB pins, groups and functionsYoshihiro Shimoda2017-09-191-0/+119
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a7795: Re-add DRIF supportDirk Behme2017-09-191-0/+291
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DRIF support for r8a7795 was initially added with commit 2d775831988 ("pinctrl: sh-pfc: r8a7795: Add DRIF support") and later dropped from the new pfc-r8a7795.c while re-naming the initial pfc-r8a7795.c to pfc-r8a7795-es1.c in commit b205914c8f8 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0"). As the DRIF doesn't differ, re-add it here. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: r8a7795: Add SDHI0-3 supportTakeshi Kihara2017-09-191-0/+275
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SDHI0-3 support for R-Car H3 ES2.0 based on a patch from the Renesas BSP. SDHI pin config is identical to H3 ES1.*. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | pinctrl: rockchip: rk3328: Fix the correct routing configDavid Wu2017-10-071-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the gmac-m1 optimization(bit10) is selected, the gpio function of gmac pins is not valid. We may use the rmii mode for gmac interface, the pins such as rx_d2, rx_d3, which the rgmii mode used, but rmii not used could be taken as gpio function. So gmac_rxd0m1 selects the bit2, and gmac_rxd0m3 select bit10 is more correct. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: rockchip: Fix the rk3399 gpio0 and gpio1 banks' drv_offset at pmu grfDavid Wu2017-10-071-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The offset of gpio0 and gpio1 bank drive strength is 0x8, not 0x4. But the mux is 0x4, we couldn't use the IOMUX_WIDTH_4BIT flag, so we give them actual offset. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | Merge branch 'pinconf-rename' into develLinus Walleij2017-10-079-39/+22Star
| |\ \ \
| | * | | pinctrl: meson: Use library functionsLinus Walleij2017-10-071-14/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These request/free functions are just reimplementations of the standard helpers in gpiolib. Delete them and replace with the helpers. Cc: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| | * | | pinctrl: bcm: nsp: Use library functionsLinus Walleij2017-10-071-19/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These request/free functions are just reimplementations of the standard helpers in gpiolib. Delete them and replace with the helpers. Acked-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| | * | | pinctrl/gpio: Unify namespace for cross-callsLinus Walleij2017-09-2210-24/+24
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pinctrl_request_gpio() and pinctrl_free_gpio() break the nice namespacing in the other cross-calls like pinctrl_gpio_foo(). Just rename them and all references so we have one namespace with all cross-calls under pinctrl_gpio_*(). Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: meson-gxbb: add missing GPIOX_22 pinJerome Brunet2017-10-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIOX_22 is declared as a gpio but the id is no present in the pin table. This hole trigger an error while reading the pingroup debugfs entry GPIOX_22 is no routed externally. For all we know, it could an internal pin of SoC Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: meson-gx: TEST_N belongs to the AO controllerJerome Brunet2017-10-052-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On meson-gx platforms, TEST_N has been incorrectly declared in the EE controller while it belongs to AO controller. Move the pin to the appropriate controller Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: meson: get rid of pin_baseJerome Brunet2017-10-055-25/+13Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pin_base was used with the manually set pin offset in meson pinctrl. This is no longer the case, pin_base is 0 on every meson pinctrl controllers and should go away. Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: meson: remove offset from pinctrlJerome Brunet2017-10-056-1741/+1697Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Offset on meson pinctrl and gpios is something that was carried from the vendor driver, where there is a weird link between the 2 controllers. Since these 2 controllers are independent, this offset adds an unnecessary complexity. This patch remove this manually set offset and rely on pinctrl to figure out the gpio base offset Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: cherryview fixed typo in commentChris Gorman2017-09-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixed typo on comment for north_community. Signed-off-by: Chris Gorman <chrisjohgorman@gmail.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: meson: fix incorrect usage of ENOSYSJerome Brunet2017-09-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ENOSYS is special and should only be used for incorrect syscall number. It is not the case here. let's use ENOTSUPP instead. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: single: make two arrays static const, reduces object code sizeColin Ian King2017-09-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't populate the read-only arrays prop2 and prop4 on the stack, instead make them static const. Makes the object code smaller by over 230 bytes: Before: text data bss dec hex filename 28235 5820 192 34247 85c7 drivers/pinctrl/pinctrl-single.o After: text data bss dec hex filename 27839 5980 192 34011 84db drivers/pinctrl/pinctrl-single.o Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl/amd: make functions amd_gpio_suspend and amd_gpio_resume staticColin Ian King2017-09-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The functions amd_gpio_suspend and amd_gpio_resume are local to the source and do not need to be in global scope, so make them static. Cleans up sparse warnings: symbol 'amd_gpio_suspend' was not declared. Should it be static? symbol 'amd_gpio_resume' was not declared. Should it be static? Signed-off-by: Colin Ian King <colin.king@canonical.com> Reviewed-by: Daniel Drake <drake@endlessm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: uniphier: make arrays static, reduces object code sizeColin Ian King2017-09-191-6/+8
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't populate const arrays on the stack, instead make them static. Makes the object code smaller nearly 1000 bytes. Also line break wide lines to avoid checkpatch warnings. Before: text data bss dec hex filename 13112 1996 0 15108 3b04 pinctrl-uniphier-core.o After: text data bss dec hex filename 11642 2476 0 14118 3726 pinctrl-uniphier-core.o Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | Merge tag 'gpio-v4.15-1' of ↵Linus Torvalds2017-11-1520-29/+27Star
|\ \ \ | | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull GPIO updates from Linus Walleij: "This is the bulk of GPIO changes for the v4.15 kernel cycle: Core: - Fix the semantics of raw GPIO to actually be raw. No inversion semantics as before, but also no open draining, and allow the raw operations to affect lines used for interrupts as the caller supposedly knows what they are doing if they are getting the big hammer. - Rewrote the __inner_function() notation calls to names that make more sense. I just find this kind of code disturbing. - Drop the .irq_base() field from the gpiochip since now all IRQs are mapped dynamically. This is nice. - Support for .get_multiple() in the core driver API. This allows us to read several GPIO lines with a single register read. This has high value for some usecases: it can be used to create oscilloscopes and signal analyzers and other things that rely on reading several lines at exactly the same instant. Also a generally nice optimization. This uses the new assign_bit() macro from the bitops lib that was ACKed by Andrew Morton and is implemented for two drivers, one of them being the generic MMIO driver so everyone using that will be able to benefit from this. - Do not allow requests of Open Drain and Open Source setting of a GPIO line simultaneously. If the hardware actually supports enabling both at the same time the electrical result would be disastrous. - A new interrupt chip core helper. This will be helpful to deal with "banked" GPIOs, which means GPIO controllers with several logical blocks of GPIO inside them. This is several gpiochips per device in the device model, in contrast to the case when there is a 1-to-1 relationship between a device and a gpiochip. New drivers: - Maxim MAX3191x industrial serializer, a very interesting piece of professional I/O hardware. - Uniphier GPIO driver. This is the GPIO block from the recent Socionext (ex Fujitsu and Panasonic) platform. - Tegra 186 driver. This is based on the new banked GPIO infrastructure. Other improvements: - Some documentation improvements. - Wakeup support for the DesignWare DWAPB GPIO controller. - Reset line support on the DesignWare DWAPB GPIO controller. - Several non-critical bug fixes and improvements for the Broadcom BRCMSTB driver. - Misc non-critical bug fixes like exotic errorpaths, removal of dead code etc. - Explicit comments on fall-through switch() statements" * tag 'gpio-v4.15-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (65 commits) gpio: tegra186: Remove tegra186_gpio_lock_class gpio: rcar: Add r8a77995 (R-Car D3) support pinctrl: bcm2835: Fix some merge fallout gpio: Fix undefined lock_dep_class gpio: Automatically add lockdep keys gpio: Introduce struct gpio_irq_chip.first gpio: Disambiguate struct gpio_irq_chip.nested gpio: Add Tegra186 support gpio: Export gpiochip_irq_{map,unmap}() gpio: Implement tighter IRQ chip integration gpio: Move lock_key into struct gpio_irq_chip gpio: Move irq_valid_mask into struct gpio_irq_chip gpio: Move irq_nested into struct gpio_irq_chip gpio: Move irq_chained_parent to struct gpio_irq_chip gpio: Move irq_default_type to struct gpio_irq_chip gpio: Move irq_handler to struct gpio_irq_chip gpio: Move irqdomain into struct gpio_irq_chip gpio: Move irqchip into struct gpio_irq_chip gpio: Introduce struct gpio_irq_chip pinctrl: armada-37xx: remove unused variable ...
| * | pinctrl: bcm2835: Fix some merge falloutLinus Walleij2017-11-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Fixing a small merge problem in BCM2835 related to the new irqchip code. Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | gpio: Move irq_valid_mask into struct gpio_irq_chipThierry Reding2017-11-082-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | gpio: Move irqdomain into struct gpio_irq_chipThierry Reding2017-11-0820-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-10-27 13:26:14 +0100