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* | pinctrl: stm32: align stm32mp157 pin namesAlexandre Torgue2019-04-231-284/+277Star
| | | | | | | | | | | | | | | | Align pins names with names provided in official stm32mp157 datasheet available on st.com. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: stm32: add package information for stm32mp157cAlexandre Torgue2019-04-232-176/+358
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds four new packages support for stm32mp157c die: STM32MP_PKG_AA: LFBGA448 (18*18), 176 IOs STM32MP_PKG_AB: LFBGA354 (16*16), 98 IOs STM32MP_PKG_AC: TFBGA361 (12*12), 148 IOs STM32MP_PKG_AD: TFBGA257 (10*10), 98 IOs Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: stm32: introduce package supportAlexandre Torgue2019-04-232-11/+65
| | | | | | | | | | | | | | | | | | | | | | | | A same SoC can be available in several packages. Differences between packages are only the numbers of available balls. In order not to write a driver for each new package, same driver (ex: pinctrl-stm32mp157.c) will be used. This patch introduces the "package" property for each pin. So on a same driver, it will be possible to indicate on which package the pin is available. The package information will be got from the device tree. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: imx8mq: Add suspend/resume opsAbel Vesa2019-04-113-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | To support pinctl hog restore after LPSR resume back, add the generic suspend/resume in pinctrl-imx along with the generic pm ops to be used by platform specific drivers. Then make use of the newly added ops in i.MX8MQ platform specific driver. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: artpec6: Drop unused function and renameLinus Walleij2019-04-111-17/+4Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pincontrol callbacks used to be symmetric: enable/disable. However for a while we only have one function that set the muxing, no disabling. Drop the unused disable function, and rename the *enable() function to *set(). Reported-by: Nathan Chancellor <natechancellor@gmail.com> Cc: YueHaibing <yuehaibing@huawei.com> Reviewed-by: Nathan Chancellor <natechancellor@gmail.com> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Added IRQF_SHARED flag for amd-pinctrl driverSandeep Singh2019-04-081-2/+2
| | | | | | | | | | | | | | | | | | | | Some of the AMD reference boards used single GPIO line for multiple devices. So added IRQF_SHARED flag in amd pinctrl driver. Signed-off-by: Sandeep Singh <Sandeep.Singh@amd.com> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> cc: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: freescale: use devm_platform_ioremap_resource() to simplify codeAnson Huang2019-04-081-3/+1Star
| | | | | | | | | | | | | | | | | | | | Use the new helper devm_platform_ioremap_resource() which wraps the platform_get_resource() and devm_ioremap_resource() together, to simplify the code. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Mukesh Ojha <mojha@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: imx: remove an unnecessary NULL checkDan Carpenter2019-04-081-1/+1
| | | | | | | | | | | | | | | | | | The address of "ipctl->pin_regs[pin_id]" can't be NULL. It's the offset into an array in the middle of a struct. This patch removes the check. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: add drive for I2C related pins on MT8183Zhiyong Tao2019-04-084-0/+131
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides the advanced drive for I2C used pins on MT8183. The detail strength specification description of the I2C pin: When E1=0/E0=0, the strength is 0.125mA. When E1=0/E0=1, the strength is 0.25mA. When E1=1/E0=0, the strength is 0.5mA. When E1=1/E0=1, the strength is 1mA. For I2C pins, there are existing generic driving setup and the above specific driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA driving adjustment in generic driving setup. But in specific driving setup, they can support 0.125/0.25/0.5/1mA adjustment. If we enable specific driving setup for I2C pins, the existing generic driving setup will be disabled. For some special features, we need the I2C pins specific driving setup. The specific driving setup is controlled by E1E0EN. So we need add extra vendor driving preperty instead of the generic driving property. We can add "mediatek,drive-strength-adv = <XXX>;" to describe the specific driving setup property. "XXX" means the value of E1E0EN. So the valid arguments of "mediatek,drive-strength-adv" are from 0 to 7. Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: axp209: Fix NULL pointer dereference after allocationAditya Pakki2019-04-081-0/+2
| | | | | | | | | | | | | | | | | | axp20x_build_funcs_groups allocates groups via devm_kcalloc and tries to dereference without checking for NULL. This patch avoids such a scenario. Signed-off-by: Aditya Pakki <pakki001@umn.edu> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: artpec6: Make two functions staticYueHaibing2019-04-041-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix sparse warnings: drivers/pinctrl/pinctrl-artpec6.c:691:5: warning: symbol 'artpec6_pmx_enable' was not declared. Should it be static? drivers/pinctrl/pinctrl-artpec6.c:705:6: warning: symbol 'artpec6_pmx_disable' was not declared. Should it be static? Signed-off-by: YueHaibing <yuehaibing@huawei.com> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Reviewed-by: Mukesh Ojha <mojha@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge tag 'sh-pfc-for-v5.2-tag1' of ↵Linus Walleij2019-04-0437-2419/+2854
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v5.2 - Add HSCIF (serial) pin groups on R-Car H1, - Add I2C[035] pin groups on R-Car M3-N, - Add CANFD pin groups on RZ/G2M and RZ/G2E, - Retain SDHI/MMC clock return path delay configuration across suspend/resume on R-Car Gen3, - More validation of pinmux tables at build and runtime, including compile-test coverage of all drivers, - Small fixes, improvements, and cleanups.
| * | pinctrl: sh-pfc: r8a77965: Add I2C{0,3,5} pins, groups and functionsTakeshi Kihara2019-04-041-24/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC. These pins are physically muxed with other pins. Therefore, setup of MOD_SEL is needed for exclusive control with other pins. [takeshi.kihara.df: add blank lines after function declarations] Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [uli: use standard macros PINMUX_IPSR_PHYS and PINMUX_IPSR_PHYS_MSEL] Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin dataUlrich Hecht2019-04-041-5/+0Star
| | | | | | | | | | | | | | | | | | | | | Pin data for I2C controllers 0, 3 and 5 is properly defined already. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a77970: Fix spacingGeert Uytterhoeven2019-04-041-6/+6
| | | | | | | | | | | | | | | | | | | | | Replace "F_(0,0)" by "F_(0, 0)". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDFTakeshi Kihara2019-04-023-35/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50 of Feb 12, 2019, the sel_ndfc MOD_SEL register bit is renamed to sel_ndf. Update the pin control drivers to reflect this. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Update R-Car E3] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}Takeshi Kihara2019-04-023-33/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the R-Car Gen3 Hardware Manual Errata for Rev 0.80 of Dec 22, 2017, and the Errata for Rev 1.50 of Dec 25, 2018, MOD_SEL0 register bits 3, 4, 17, and 18 are renamed from SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}. Update the pin control drivers to reflect this. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitionsTakeshi Kihara2019-04-025-76/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50 of Feb 12, 2019, the RTS{0,1,3,4}_#/TANS pin names defined in the GPSR and IPSR registers are renamed to RTS{0,1,3,4}_#. This patch updates the pin control drivers to reflect this. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Update R-Car H3 ES1.x, V3M, V3H, and D3] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pinTakeshi Kihara2019-04-026-12/+6Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Jun 4, 2018, the CC5_OSCOUT pin is removed. Update the pin control drivers to reflect this. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Update R-Car V3M, V3H] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: rcar-gen3: Remove HDMI CEC pins, groups, and functionsTakeshi Kihara2019-04-024-97/+26Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The HDMI CEC function is not supported by the R-Car Gen3 Hardware Manual Rev 1.00. Therefore, delete the corresponding pin groups and functions, and rename the HDMI[01]_CEC definitions to match their GPIO functionality. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Squashed several commits] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and SSI_WS2Takeshi Kihara2019-04-021-11/+9Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug 24, 2018, there is no need to configure MOD_SEL1 bit30 when the SSI_SCK2_{A,B} or SSI_WS2_{A,B} pin functions are selected. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Remove now unused definitions, mark MOD_SEL1 bit30 reserved] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_DTakeshi Kihara2019-04-021-5/+4Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug 24, 2018, there is no need to configure MOD_SEL1 bit31 when the SIM0_D_{A,B} pin function is selected. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Remove now unused definitions, mark MOD_SEL1 bit31 reserved] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_NTakeshi Kihara2019-04-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug 24, 2018, the MOD_SEL0 bit16 must be set to 0 when the NFALE_A and NFRB_N_A pin functions are selected. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: Improve PINMUX_IPSR_PHYS() documentationGeert Uytterhoeven2019-04-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | - The IPSR field is meant for documentation only, - The function name refers to the pin function, not to the IPSR field. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * | pinctrl: rza1: Remove unneeded spinlock acquisitionsGeert Uytterhoeven2019-04-021-16/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | rza1_get_bit() is just a single register read. Hence there's no need to synchronize it with other register writes to the same bank. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Jacopo Mondi <jacopo@jmondi.org>
| * | pinctrl: sh-pfc: Validate enum IDs for regs with variable-width fieldsGeert Uytterhoeven2019-04-022-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a run-time check to the PINMUX_CFG_REG_VAR() macro, to ensure the number of provided enum IDs is correct. This cannot be done at build time, as the number of values depends on the variable-width fields in the config register. This helps catching bugs early. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: Validate enum IDs for regs with fixed-width fieldsGeert Uytterhoeven2019-04-021-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add build-time checks to the PINMUX_CFG_REG() and PINMUX_DATA_REG() macros, to ensure the number of provided enum IDs is correct. This helps catching bugs early. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: Absorb enum IDs in PINMUX_DATA_REG() macroGeert Uytterhoeven2019-04-0216-420/+420
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the PINMUX_DATA_REG() macro must be followed by initialization data, specifying all enum IDs. Hence the macro itself does not know anything about the enum IDs, preventing the macro from performing any validation on it. Make the macro accept the enum IDs as a parameter, and update all users. Note that array data enclosed by curly braces cannot be passed to a macro as a parameter, hence the enum IDs are wrapped using the GROUP() macro. No functional changes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macroGeert Uytterhoeven2019-04-0218-402/+572
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the PINMUX_CFG_REG_VAR() macro must be followed by initialization data, specifying all enum IDs. Hence the macro itself does not know anything about the enum IDs, preventing the macro from performing any validation on it. Make the macro accept the enum IDs as a parameter, and update all users. Note that array data enclosed by curly braces cannot be passed to a macro as a parameter, hence both the register field widths and the enum IDs are wrapped using the GROUP() macro. No functional changes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macroGeert Uytterhoeven2019-04-0232-1128/+1137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the PINMUX_CFG_REG() macro must be followed by initialization data, specifying all enum IDs. Hence the macro itself does not know anything about the enum IDs, preventing the macro from performing any validation on it. Make the macro accept the enum IDs as a parameter, and update all users. Note that array data enclosed by curly braces cannot be passed to a macro as a parameter, hence the enum IDs are wrapped using a new macro GROUPS(). No functional changes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: Allow compile-testing of all driversGeert Uytterhoeven2019-04-022-99/+90Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable compile-testing of all Renesas SuperH and ARM pin control drivers, in a similar way as was done before for clock and SoC drivers in commits 371dd373c6edd557 ("clk: renesas: Allow compile-testing of all (sub)drivers") and 8be381a131c29c47 ("soc: renesas: Rework Kconfig and Makefile logic"). The SuperH pin control drivers need specific include files, hence make sure they are always found when compile-testing. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: Add missing #include <linux/errno.h>Geert Uytterhoeven2019-04-0212-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Source files using -Exxx error codes should include <linux/errno.h>. On ARM, this header file is included indirectly; on SuperH, it is not, leading to "error: ‘EINVAL’ undeclared" failures when enabling compile-testing later. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: Introduce PINCTRL_SH_FUNC_GPIO helper symbolGeert Uytterhoeven2019-04-023-17/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pinctrl drivers for SuperH platforms use legacy function GPIOs. Currently this support is compiled in based on the SUPERH platform dependency, which hinders the introduction of compile-testing support for the affected pinctrl drivers. Introduce a new Kconfig symbol PINCTRL_SH_FUNC_GPIO, which is auto-selected when needed. This symbol in turn selects PINCTRL_SH_PFC_GPIO, to reduce the number of per-driver selects. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: Validate pinmux tables at runtime when debuggingGeert Uytterhoeven2019-04-021-0/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Perform some basic sanity checks on all built-in pinmux tables when DEBUG is defined, to help catching bugs early. For now the following checks are included: - Check register and field widths in descriptors for config registers with variable-width fields, - Check relations between pin groups and functions: - All pin functions must refer to existing pin groups, - All pin groups must be referred to by a pin function, - Warn if a pin group is referred to by multiple pin functions (which is OK for backwards-compatibility aliases), - Provide suggestions for reducing table sizes: reserved fields of more than 3 bits can better be split in smaller subfields, as the storage need is proportional to the square of the width of the (sub)field, Note that a dummy non-matching entry is added to the DT match table for checking r8a7795es1_pinmux_info, as R-Car H3 ES1.0 is matched using soc_device_match() in r8a7795_pinmux_init(), instead of by the DT match table. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resumeMarek Vasut2019-03-188-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | The TDSELCTRL register is responsible for configuring the SDHI/MMC clock return path delay and may be adjusted by the bootloader. Retain the value across suspend/resume to prevent hardware instability after resume. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a77990: Move CANFD pin groups and functionsFabrizio Castro2019-03-181-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | CANFD is found also on the R8A774C0, therefore move CANFD pin groups and functions to "common". Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7796: Move CANFD pin groups and functionsFabrizio Castro2019-03-181-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CANFD is found also on the R8A774A1, therefore move CANFD pin groups and functions to "common". Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7779: Add HSCIF0/1 pinsUlrich Hecht2019-03-181-0/+118
| | | | | | | | | | | | | | | | | | | | | | | | Adds HSCIF0 and HSCIF1 pins, groups and functions for R8A7779. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a77990: Rename IOCTRLx registersGeert Uytterhoeven2019-03-181-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The R-Car Gen3 HardWare Manual Errata for Rev. 1.00 (Jul 2, 2018) renamed the various miscellaneous I/O control registers (IOCTRLx) on R-Car E3, to reflect better their actual purposes, and matching other SoCs. Update the code to match this. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
| * | pinctrl: sh-pfc: r8a77980: Rename IOCTRLx registersGeert Uytterhoeven2019-03-181-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The R-Car Gen3 HardWare Manual Errata for Rev. 1.00 (Jul 2, 2018) renamed the various miscellaneous I/O control registers (IOCTRLx) on R-Car V3H, to reflect better their actual purposes, and matching other SoCs. Update the code to match this. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
| * | pinctrl: sh-pfc: r8a77970: Rename IOCTRLx registersGeert Uytterhoeven2019-03-181-8/+8
| |/ | | | | | | | | | | | | | | | | | | | | | | The R-Car Gen3 HardWare Manual Errata for Rev. 1.00 (Jul 2, 2018) renamed the various miscellaneous I/O control registers (IOCTRLx) on R-Car V3M, to reflect better their actual purposes, and matching other SoCs. Update the code to match this. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
* | pinctrl: fsl: Make pinctrl_ipc_handle staticYueHaibing2019-04-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | Fix sparse warning: drivers/pinctrl/freescale/pinctrl-scu.c:38:19: warning: symbol 'pinctrl_ipc_handle' was not declared. Should it be static? Signed-off-by: YueHaibing <yuehaibing@huawei.com> Reviewed-by: Mukesh Ojha <mojha@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: lochnagar: Add support for the Cirrus Logic LochnagarCharles Keepax2019-04-043-0/+1247
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lochnagar is an evaluation and development board for Cirrus Logic Smart CODEC and Amp devices. It allows the connection of most Cirrus Logic devices on mini-cards, as well as allowing connection of various application processor systems to provide a full evaluation platform. This driver supports the board controller chip on the Lochnagar board. Lochnagar provides many pins which can generally be used for an audio function such as an AIF or a PDM interface, but also as GPIOs. Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: sunxi: Allow to disable pinctrl driversMaxime Ripard2019-04-041-19/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Our pinctrl drivers are consisting of some common code, and big pin tables that are SoC-specific. This is fine in most cases, but when you want to reduce the size of the particular kernel image, those big tables are, well, quite big. We haven't had the option to disable them in the past since they were hidden Kconfig options based on the SoC support. However, that granularity isn't great since we don't have one Kconfig option per-SoC, but rather one by family. Make those options selectable by the user so that they can disable it if needed, while keeping the current default to not change the standard case. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: sunxi: Declare set_config on the GPIO chipMaxime Ripard2019-04-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Our pin controller can configure the pins no matter how they are muxed, so it makes sense to allow this for GPIOs as well. Add the generic set_config function so that we can rely on the existing pinctrl code we have. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: sunxi: Fix variable assignment syntaxMaxime Ripard2019-04-041-10/+10
| | | | | | | | | | | | | | | | | | | | | | Lines are usually ended with a semi-column in C, yet this was copied from a structure declaration to the init variant while keeping the comma at the end. Make sure we have a normal syntax, instead of multiple assignments. Fixes: d83c82ce7ccd ("pinctrl: sunxi: support multiple pin controller") Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: sunxi: implement pin_config_setMaxime Ripard2019-04-041-6/+13
|/ | | | | | | | | | | The sunxi pinctrl only implements the pin_config_group_set callback at the moment, whereas the gpiochip_generic_config function relies on pin_config_set. Rework the functions a little to support pin_config_set, and rely on it for pin_config_group_set. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v5.1-1' of ↵Linus Torvalds2019-03-1146-801/+2274
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is a calm cycle, not much happened this time around: not even much incremental development. Some three new drivers, that is all. No core changes. New drivers: - NXP (ex Freescale) i.MX 8QM driver. - NXP (ex Freescale) i.MX 8MM driver. - AT91 SAM9X60 subdriver. Improvements: - Support for external interrups (EINT) on Mediatek virtual GPIOs. - Make BCM2835 pin config fully generic. - Lots of Renesas SH-PFC incremental improvements" * tag 'pinctrl-v5.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (70 commits) pinctrl: imx: fix scu link errors dt-bindings: pinctrl: Document the i.MX50 IOMUXC binding pinctrl: qcom: spmi-gpio: Reorder debug print pinctrl: nomadik: fix possible object reference leak pinctrl: stm32: return error upon hwspinlock failure pinctrl: stm32: fix memory leak issue pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions pinctrl: sh-pfc: Validate fixed-size field widths at build time pinctrl: sh-pfc: sh73a0: Fix fsic_spdif pin groups pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group pinctrl: sh-pfc: emev2: Add missing pinmux functions pinctrl: sunxi: Support I/O bias voltage setting on A80 pinctrl: ingenic: Add LCD pins for the JZ4725B SoC pinctrl: samsung: Remove legacy API for handling external wakeup interrupts mask pinctrl: bcm2835: Direct GPIO config changes to generic pinctrl pinctrl: bcm2835: declare pin config as generic pinctrl: qcom: qcs404: Drop unused UFS_RESET macro dt-bindings: add documentation for slew rate ...
| * pinctrl: imx: fix scu link errorsAnders Roxell2019-03-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently PINCTRL_IMX8QM and PINCTRL_IMX8QXP will select PINCTRL_IMX_SCU. However, PINCTRL_IMX_SCU may not be valid due to it depends on IMX_MBOX. Then we may meet the following link errors: ld: drivers/pinctrl/freescale/pinctrl-scu.o: in function `imx_pinctrl_sc_ipc_init': pinctrl-scu.c:(.text+0x10): undefined reference to `imx_scu_get_handle' ld: pinctrl-scu.c:(.text+0x10): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `imx_scu_get_handle' ld: drivers/pinctrl/freescale/pinctrl-scu.o: in function `imx_pinconf_get_scu': pinctrl-scu.c:(.text+0xa0): undefined reference to `imx_scu_call_rpc' ld: pinctrl-scu.c:(.text+0xa0): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `imx_scu_call_rpc' ld: drivers/pinctrl/freescale/pinctrl-scu.o: in function `imx_pinconf_set_scu': pinctrl-scu.c:(.text+0x1b4): undefined reference to `imx_scu_call_rpc' ld: pinctrl-scu.c:(.text+0x1b4): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `imx_scu_call_rpc' ld: drivers/pinctrl/freescale/pinctrl-imx8qxp.o: in function `imx8qxp_pinctrl_probe': pinctrl-imx8qxp.c:(.text+0x28): undefined reference to `imx_pinctrl_probe' ld: pinctrl-imx8qxp.c:(.text+0x28): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `imx_pinctrl_probe' Rework so that PINCTRL_IMX8QM and PINCTRL_IMX8QXP depends on IMX_SCU as well in case they're wrongly enabled. Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Anders Roxell <anders.roxell@linaro.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: spmi-gpio: Reorder debug printBjorn Andersson2019-02-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's reasonable to expect that people turn to the "gpio" debugfs file to first and foremost learn about the direction and value of a gpio, and second to that about it's pinconf. So reorder the value so each line reads: gpioN: direction value ... This also makes it consistent with the TLMM pinctrl driver's output in the same dump. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-11-19 09:29:58 +0100