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* Merge tag 'pinctrl-v4.13-2' of ↵Linus Torvalds2017-08-096-15/+37
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control fixes from Linus Walleij: "These are the pin control fixes I have gathered since the return from my vacation. They boiled in -next a while so let's get them in. Apart from the documentation build it is purely driver fixes. Which is nice. The Intel fixes seem kind of important. - Fix the documentation build as the docs were moved - Correct the UART pin list on the Intel Merrifield - Fix pin assignment and number of pins on the Marvell Armada 37xx pin controller - Cover the Setzer models in the Chromebook DMI quirk in the Intel cheryview driver so they start working - Add the missing "sim" function to the sunxi driver - Fix USB pin definitions on Uniphier Pro4 - Smatch fix for invalid reference in the zx pin control driver" * tag 'pinctrl-v4.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: generic: update references to Documentation/pinctrl.txt pinctrl: intel: merrifield: Correct UART pin lists pinctrl: armada-37xx: Fix number of pin in south bridge pinctrl: armada-37xx: Fix the pin 23 on south bridge pinctrl: cherryview: Add Setzer models to the Chromebook DMI quirk pinctrl: sunxi: add a missing function of A10/A20 pinctrl driver pinctrl: uniphier: fix USB3 pin assignment for Pro4 pinctrl: zte: fix dereference of 'data' in zx_set_mux()
| * pinctrl: intel: merrifield: Correct UART pin listsAndy Shevchenko2017-08-071-3/+3
| | | | | | | | | | | | | | | | | | | | UART pin lists consist GPIO numbers which is simply wrong. Replace it by pin numbers. Fixes: 4e80c8f50574 ("pinctrl: intel: Add Intel Merrifield pin controller support") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: armada-37xx: Fix number of pin in south bridgeGregory CLEMENT2017-08-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the south bridge we have pin from to 29, so it gives 30 pins (and not 29). Without this patch the kernel complain with the following traces: cat /sys/kernel/debug/pinctrl/d0018800.pinctrl/pingroups [ 154.530205] armada-37xx-pinctrl d0018800.pinctrl: failed to get pin(29) name [ 154.537567] ------------[ cut here ]------------ [ 154.542348] WARNING: CPU: 1 PID: 1347 at /home/gclement/open/kernel/marvell-mainline-linux/drivers/pinctrl/core.c:1610 pinctrl_groups_show+0x15c/0x1a0 [ 154.555918] Modules linked in: [ 154.558890] CPU: 1 PID: 1347 Comm: cat Tainted: G W 4.13.0-rc1-00001-g19e1b9fa219d #525 [ 154.568316] Hardware name: Marvell Armada 3720 Development Board DB-88F3720-DDR3 (DT) [ 154.576311] task: ffff80001d32d100 task.stack: ffff80001bdc0000 [ 154.583048] PC is at pinctrl_groups_show+0x15c/0x1a0 [ 154.587816] LR is at pinctrl_groups_show+0x148/0x1a0 [ 154.592847] pc : [<ffff0000083e3adc>] lr : [<ffff0000083e3ac8>] pstate: 00000145 [ 154.600840] sp : ffff80001bdc3c80 [ 154.604255] x29: ffff80001bdc3c80 x28: 00000000f7750000 [ 154.609825] x27: ffff80001d05d198 x26: 0000000000000009 [ 154.615224] x25: ffff0000089ead20 x24: 0000000000000002 [ 154.620705] x23: ffff000008c8e1d0 x22: ffff80001be55700 [ 154.626187] x21: ffff80001d05d100 x20: 0000000000000005 [ 154.631667] x19: 0000000000000006 x18: 0000000000000010 [ 154.637238] x17: 0000000000000000 x16: ffff0000081fc4b8 [ 154.642726] x15: 0000000000000006 x14: ffff0000899e537f [ 154.648214] x13: ffff0000099e538d x12: 206f742064656c69 [ 154.653613] x11: 6166203a6c727463 x10: 0000000005f5e0ff [ 154.659094] x9 : ffff80001bdc38c0 x8 : 286e697020746567 [ 154.664576] x7 : ffff000008551870 x6 : 000000000000011b [ 154.670146] x5 : 0000000000000000 x4 : 0000000000000000 [ 154.675544] x3 : 0000000000000000 x2 : 0000000000000000 [ 154.681025] x1 : ffff000008c8e1d0 x0 : ffff80001be55700 [ 154.686507] Call trace: [ 154.688668] Exception stack(0xffff80001bdc3ab0 to 0xffff80001bdc3be0) [ 154.695224] 3aa0: 0000000000000006 0001000000000000 [ 154.703310] 3ac0: ffff80001bdc3c80 ffff0000083e3adc ffff80001bdc3bb0 00000000ffffffd8 [ 154.711304] 3ae0: 4554535953425553 6f6674616c703d4d 4349564544006d72 6674616c702b3d45 [ 154.719478] 3b00: 313030643a6d726f 6e69702e30303838 ffff80006c727463 ffff0000089635d8 [ 154.727562] 3b20: ffff80001d1ca0cb ffff000008af0fa4 ffff80001bdc3b40 ffff000008c8e1dc [ 154.735648] 3b40: ffff80001bdc3bc0 ffff000008223174 ffff80001be55700 ffff000008c8e1d0 [ 154.743731] 3b60: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 [ 154.752354] 3b80: 000000000000011b ffff000008551870 286e697020746567 ffff80001bdc38c0 [ 154.760446] 3ba0: 0000000005f5e0ff 6166203a6c727463 206f742064656c69 ffff0000099e538d [ 154.767910] 3bc0: ffff0000899e537f 0000000000000006 ffff0000081fc4b8 0000000000000000 [ 154.776085] [<ffff0000083e3adc>] pinctrl_groups_show+0x15c/0x1a0 [ 154.782823] [<ffff000008222abc>] seq_read+0x184/0x460 [ 154.787505] [<ffff000008344120>] full_proxy_read+0x60/0xa8 [ 154.793431] [<ffff0000081f9bec>] __vfs_read+0x1c/0x110 [ 154.799001] [<ffff0000081faff4>] vfs_read+0x84/0x140 [ 154.803860] [<ffff0000081fc4fc>] SyS_read+0x44/0xa0 [ 154.808983] [<ffff000008082f30>] el0_svc_naked+0x24/0x28 [ 154.814459] ---[ end trace 4cbb00a92d616b95 ]--- Cc: stable@vger.kernel.org Fixes: 87466ccd9401 ("pinctrl: armada-37xx: Add pin controller support for Armada 37xx") Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: armada-37xx: Fix the pin 23 on south bridgeGregory CLEMENT2017-08-071-6/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin 23 on South bridge does not belong to the rgmii group. It belongs to a separate group which can have 3 functions. Due to this the fix also have to update the way the functions are managed. Until now each groups used NB_FUNCS(which was 2) functions. For the mpp23, 3 functions are available but it is the only group which needs it, so on the loop involving NB_FUNCS an extra test was added to handle only the functions added. The bug was visible with the merge of the commit 07d065abf93d "arm64: dts: marvell: armada-3720-db: Add vqmmc regulator for SD slot", the gpio regulator used the gpio 23, due to this the whole rgmii group was setup to gpio which broke the Ethernet support on the Armada 3720 DB board. Thanks to this patch, the UHS SD cards (which need the vqmmc) _and_ the Ethernet work again. Cc: stable@vger.kernel.org Fixes: 87466ccd9401 ("pinctrl: armada-37xx: Add pin controller support for Armada 37xx") Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: cherryview: Add Setzer models to the Chromebook DMI quirkAndy Shevchenko2017-08-031-0/+7
| | | | | | | | | | | | | | | | | | | | | | Add one more model to the Chromebook DMI quirk to make it working again. Link: https://bugzilla.kernel.org/show_bug.cgi?id=194945 Fixes: 2a8209fa6823 ("pinctrl: cherryview: Extend the Chromebook DMI quirk to Intel_Strago systems") Reported-by: mail@abhishek.geek.nz Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sunxi: add a missing function of A10/A20 pinctrl driverIcenowy Zheng2017-07-311-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PH16 pin has a function with mux id 0x5, which is the DET pin of the "sim" (smart card reader) IP block. This function is missing in old versions of A10/A20 SoCs' datasheets and user manuals, so it's also missing in the old drivers. The newest A10 Datasheet V1.70 and A20 Datasheet V1.41 contain this pin function, and it's discovered during implementing R40 pinctrl driver. Add it to the driver. As we now merged A20 pinctrl driver to the A10 one, we need to only fix the A10 driver now. Fixes: f2821b1ca3a2 ("pinctrl: sunxi: Move Allwinner A10 pinctrl driver to a driver of its own") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: uniphier: fix USB3 pin assignment for Pro4Kunihiko Hayashi2017-07-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to pinctrl assignment for Pro4, each definition of USB#2 and USB#3 are as follows. 184: USB2VBUS 185: USB2OD 186: USB2ID 187: USB3VBUS 188: USB3OD USB#2 has an additional pin "USB2ID", but the chip doesn't use this pin while in host-mode. Considering this pin, the pin definitions for USB#3 should be {187, 188}. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: zte: fix dereference of 'data' in zx_set_mux()Shawn Guo2017-07-311-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | It fixes the following Smatch complaint: drivers/pinctrl/zte/pinctrl-zx.c:76 zx_set_mux() warn: variable dereferenced before check 'data' (see line 67) Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Fixes: cbff0c4d27f4 ("pinctrl: add ZTE ZX pinctrl driver support") Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: stm32: select IRQ_DOMAIN_HIERARCHY instead of depends onMasahiro Yamada2017-08-011-4/+5
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Drivers that need IRQ_DOMAIN_HIERARCHY should "select" it, but drivers/pinctrl/stm32/Kconfig is the only exception that uses "depends on" syntax. This prevents GPIO drivers from select'ing IRQ_DOMAIN_HIERARCHY. For example, if I add "select IRQ_DOMAIN_HIERARCHY" to GPIO_XGENE_SB, I get the following recursive dependency error. drivers/gpio/Kconfig:13:error: recursive dependency detected! For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/gpio/Kconfig:13: symbol GPIOLIB is selected by PINCTRL_STM32 For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/pinctrl/stm32/Kconfig:3: symbol PINCTRL_STM32 is selected by PINCTRL_STM32F429 For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/pinctrl/stm32/Kconfig:11: symbol PINCTRL_STM32F429 depends on IRQ_DOMAIN_HIERARCHY For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" kernel/irq/Kconfig:67: symbol IRQ_DOMAIN_HIERARCHY is selected by GPIO_XGENE_SB For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/gpio/Kconfig:502: symbol GPIO_XGENE_SB depends on GPIOLIB Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v4.13-1' of ↵Linus Torvalds2017-07-0690-6658/+13076
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the big bulk of pin control changes for the v4.13 series: Core: - The documentation is moved over to RST. - We now have agreed bindings for enabling input and output buffers without actually enabling input and/or output on a pin. We are chiseling out some details of pin control electronics. New drivers: - ZTE ZX - Renesas RZA1 - MIPS Ingenic JZ47xx: also switch over existing drivers in the tree to use this pin controller and consolidate earlier spread out code. - Microschip MCP23S08: this driver is migrated from the GPIO subsystem and totally rewritten to use proper pin control. All users are switched over. New subdrivers: - Renesas R8A7743 and R8A7745. - Allwinner Sunxi A83T R_PIO. - Marvell MVEBU Armada CP110 and AP806. - Intel Cannon Lake PCH. - Qualcomm IPQ8074. Notable improvements: - IRQ support on the Marvell MVEBU Armada 37xx. - Meson driver supports HDMI CEC, AO, I2S, SPDIF and PWM. - Rockchip driver now supports iomux-route switching for RK3228, RK3328 and RK3399. - Rockchip A10 and A20 are merged into a single driver. - STM32 has improved GPIO support. - Samsung Exynos drivers are split per ARMv7 and ARMv8. - Marvell MVEBU is converted to use regmap for register access. Maintenance: - Several Renesas SH-PFC refactorings and updates. - Serious code size cut for Mediatek MT7623. - Misc janitorial and MAINTAINERS fixes" * tag 'pinctrl-v4.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (137 commits) pinctrl: samsung: Remove bogus irq_[un]mask from resource management pinctrl: rza1: make structures rza1_gpiochip_template and rza1_pinmux_ops static pinctrl: rza1: Remove unneeded wrong check for wrong variable pinctrl: qcom: Add ipq8074 pinctrl driver pinctrl: freescale: imx7d: make of_device_ids const. pinctrl: DT: extend the pinmux property to support integers array pinctrl: generic: Add output-enable property pinctrl: armada-37xx: Fix number of pin in sdio_sb pinctrl: armada-37xx: Fix uart2 group selection register mask pinctrl: bcm2835: Avoid warning from __irq_do_set_handler pinctrl: sh-pfc: r8a7795: Add PWM support MAINTAINERS: Add Qualcomm pinctrl drivers section arm: dts: dt-bindings: Add Renesas RZ/A1 pinctrl header dt-bindings: pinctrl: Add RZ/A1 bindings doc pinctrl: Renesas RZ/A1 pin and gpio controller pinctrl: sh-pfc: r8a7792: Add SCIF1 and SCIF2 pin groups pinctrl.txt: move it to the driver-api book pinctrl: ingenic: checking for NULL instead of IS_ERR() pinctrl: uniphier: fix WARN_ON() of pingroups dump on LD20 pinctrl: uniphier: fix WARN_ON() of pingroups dump on LD11 ...
| * pinctrl: samsung: Remove bogus irq_[un]mask from resource managementThomas Gleixner2017-06-301-4/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The irq chip callbacks irq_request/release_resources() have absolutely no business with masking and unmasking the irq. The core code unmasks the interrupt after complete setup and masks it before invoking irq_release_resources(). The unmask is actually harmful as it happens before the interrupt is completely initialized in __setup_irq(). Remove it. Fixes: f6a8249f9e55 ("pinctrl: exynos: Lock GPIOs as interrupts when used as EINTs") Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Kukjin Kim <kgene@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-gpio@vger.kernel.org Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: rza1: make structures rza1_gpiochip_template and rza1_pinmux_ops staticColin Ian King2017-06-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | structures rza1_gpiochip_template and rza1_pinmux_ops do not need to be in global scope, so make them static. Cleans up sparse warnings: symbol 'rza1_gpiochip_template' was not declared. Should it be static? symbol 'rza1_pinmux_ops' was not declared. Should it be static? Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: rza1: Remove unneeded wrong check for wrong variableGeert Uytterhoeven2017-06-301-3/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Depending on compiler version: drivers/pinctrl/pinctrl-rza1.c: In function ‘rza1_pinctrl_probe’: drivers/pinctrl/pinctrl-rza1.c:1260:5: warning: ‘ret’ may be used uninitialized in this function [-Wmaybe-uninitialized] if (ret) ^ Indeed, the result returned by platform_get_resource() was stored in "res", not "ret". In addition, the correct error check would be "if (!res)", as platform_get_resource() does not return an error code, but returns NULL on failure. However, as devm_ioremap_resource() verifies the validity of the passed resource pointer anyway, the check can just be removed. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Fixes: 5a49b644b3075f88 ("pinctrl: Renesas RZ/A1 pin and gpio controller") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: Add ipq8074 pinctrl driverVaradarajan Narayanan2017-06-293-0/+1087
| | | | | | | | | | | | | | | | | | | | | | Add initial pinctrl driver to support pin configuration with pinctrl framework for ipq8074. Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * Merge tag 'sh-pfc-for-v4.13-tag2' of ↵Linus Walleij2017-06-295-0/+1743
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.13 (take two) - Add SCIF1 and SCIF2 pin groups for R-Car V2H, - Add EtherAVB, DU parallel RGB output, and PWM pin groups for R-Car H3 ES2.0, - Add pin and gpio controller support for RZ/A1.
| | * pinctrl: sh-pfc: r8a7795: Add PWM supportLaurent Pinchart2017-06-261-0/+153
| | | | | | | | | | | | | | | | | | | | | Add pinctrl support for the PWM[0-6] pins. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: Renesas RZ/A1 pin and gpio controllerJacopo Mondi2017-06-233-0/+1323
| | | | | | | | | | | | | | | | | | | | | | | | Add combined gpio and pin controller driver for Renesas RZ/A1 r7s72100 SoC. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7792: Add SCIF1 and SCIF2 pin groupsUlrich Hecht2017-06-211-0/+55
| | | | | | | | | | | | | | | | | | | | | Add SCIF1 and SCIF2 pin groups to the R8A7792 PFC driver. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7795: Add DU parallel RGB output supportLaurent Pinchart2017-06-161-0/+101
| | | | | | | | | | | | | | | | | | | | | | | | The H3 ES1.x and H3 ES2.0 have identical pinmuxing for the parallel RGB output support. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * pinctrl: sh-pfc: r8a7795: Add EtherAVB pins, groups and functionGeert Uytterhoeven2017-06-131-0/+111
| | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups, and a function for EtherAVB on R-Car H3 ES2.0. Extracted from a big patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: freescale: imx7d: make of_device_ids const.Arvind Yadav2017-06-291-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | of_device_ids are not supposed to change at runtime. All functions working with of_device_ids provided by <linux/of.h> work with const of_device_ids. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: generic: Add output-enable propertyJacopo Mondi2017-06-291-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add output-enable generic pin configuration property. This properties allows enabling/disabling pin's output capabilities without actually driving any value on the line. Acked-by: Rob Herring <robh@kernel.org> [Added inline elaborations on buffer enabling/disabling] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | Merge tag 'v4.12-rc7' into develLinus Walleij2017-06-297-97/+80Star
| |\ \ | | | | | | | | | | | | Linux 4.12-rc7
| * | | pinctrl: armada-37xx: Fix number of pin in sdio_sbGregory CLEMENT2017-06-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sdio_sb group is composed of 6 pins and not 5. Reported-by: Ken Ma <make@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: armada-37xx: Fix uart2 group selection register maskKen Ma2017-06-291-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If north bridge selection register bit1 is clear, pins [10:8] are for SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn and CTSn, so bit1 should be added to uart2 group and it must be set for both "gpio" and "uart" functions of uart2 group. Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: bcm2835: Avoid warning from __irq_do_set_handlerStefan Wahren2017-06-291-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We get a warning during boot with enabled EARLY_PRINTK that we try to set a irq_chip without data. This is caused by ignoring the return value of irq_of_parse_and_map(). So avoid calling gpiochip_set_chained_irqchip() in error case. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Fixes: 85ae9e512f43 ("pinctrl: bcm2835: switch to GPIOLIB_IRQCHIP") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: ingenic: checking for NULL instead of IS_ERR()Dan Carpenter2017-06-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devm_pinctrl_register() returns error pointers, it doesn't return NULL. Fixes: b5c23aa46537 ("pinctrl: add a pinctrl driver for the Ingenic jz47xx SoCs") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: uniphier: fix WARN_ON() of pingroups dump on LD20Masahiro Yamada2017-06-201-189/+194
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pingroups dump of debugfs hits WARN_ON() in pinctrl_groups_show(). Filling non-existing ports with '-1' turned out a bad idea. Fixes: 336306ee1f2d ("pinctrl: uniphier: add UniPhier PH1-LD20 pinctrl driver") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: uniphier: fix WARN_ON() of pingroups dump on LD11Masahiro Yamada2017-06-201-172/+192
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pingroups dump of debugfs hits WARN_ON() in pinctrl_groups_show(). Filling non-existing ports with '-1' turned out a bad idea. Fixes: 70f2f9c4cf25 ("pinctrl: uniphier: add UniPhier PH1-LD11 pinctrl driver") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | Merge tag 'samsung-pinctrl-4.13' of ↵Linus Walleij2017-06-2010-1197/+1269
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers update for v4.13: 1. Split drivers per ARMv7 and ARMv8 architectures because there is no need to compile everything on each of them. 2. Fix for possible NULL-pointer dereference after memory allocation failure. 3. Cleanups (silencing cast warnings, constify, removal of unneeded casts, removal of modular boiler-plate).
| | * | | pinctrl: samsung: Explicitly cast pointer returned by of_iomap() to iomemKrzysztof Kozlowski2017-06-071-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For S5Pv210 retention control, the driver stores the iomem pointer from of_iomap() under a void pointer member. This makes sparse unhappy: drivers/pinctrl/samsung/pinctrl-exynos.c:664:36: warning: incorrect type in argument 1 (different address spaces) drivers/pinctrl/samsung/pinctrl-exynos.c:664:36: expected void const volatile [noderef] <asn:2>*addr drivers/pinctrl/samsung/pinctrl-exynos.c:664:36: got void * The iomem pointer is used safely (stored under priv by s5pv210_retention_init(), used by s5pv210_retention_disable()) thus we can add explicit casts to iomem to silence the warning. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
| | * | | pinctrl: samsung: Handle memory allocation failure during wakeup banks initKrzysztof Kozlowski2017-06-071-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check if kmemdup failed during wakeup banks initialization. Otherwise NULL pointer would be stored under "irq_chip" member of bank and later dereferenced in interrupt handler. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
| | * | | pinctrl: samsung: Constify wakeup driver specific dataKrzysztof Kozlowski2017-06-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Static exynos_irq_chip structures, containing driver specific data, are referenced only through opaque data pointer in const of_device_id table. The contents of pointed memory (exynos_irq_chip structure itself) is then copied with kmemdup() during wakeup initialization so exynos_irq_chip can be made const for code safenes. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
| | * | | pinctrl: samsung: Split Exynos drivers per ARMv7 and ARMv8Krzysztof Kozlowski2017-06-077-1159/+1245
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Exynos pinctrl drivers contain pretty big per-SoC data structures. The pinctrl-exynos object file contained code and data for both ARMv7 and ARMv8 SoCs thus it grew big. There will not be a shared image between ARMv7 and ARMv8 so there is no need to combine all of this into one driver. Splitting the data allows to make it more granular (e.g. code related to ARMv8 Exynos is self-contained), slightly speed up the compilation and reduce the effective size of compiled kernel. The common data structures and functions reside still in existing pinctrl-exynos.c. Only the SoC-specific parts were moved out to new files. Except marking few functions non-static and adding them to header, there were no functional changes in the code. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
| | * | | pinctrl: samsung: Add include guard to local headerKrzysztof Kozlowski2017-05-241-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pinctrl-exynos.h header is included only once so till now it did not require an include guard. However adding such is harmless and makes code prepared for more inclusions. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
| | * | | pinctrl: samsung: Clean up modular vs. non-modular distinctionsPaul Gortmaker2017-05-235-27/+6Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixups here tend to be more all over the map vs. some of the other repeated/systematic ones we've seen elsewhere. We remove module.h from code that isn't doing anything modular at all; if they have __init sections, then replace it with init.h A couple drivers have module_exit() code that is essentially orphaned, and so we remove that. There are no module_init replacements, so we have no concerns wrt. initcall ordering changes as per some of the other cleanups. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
| | * | | pinctrl: samsung: Remove unneeded (void *) casts in of_match_tableMasahiro Yamada2017-05-151-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_device_id::data is an opaque pointer. No explicit cast is needed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
| * | | | pinctrl: mvebu: add driver for Armada CP110 pinctrlHanna Hawa2017-06-163-0/+692
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a pinctrl driver for the CP110 part of the Marvell Armada 7K and 8K SoCs. The Armada 7K has a single CP110, where almost all the MPP pins are available. On the other side, the Armada 8K has two CP110, and the available MPPs are split between the master CP110 (MPPs 32 to 62) and the slave CP110 (MPPs 0 to 31). The register interface to control the MPPs is however the same as all other mvebu SoCs, so we can reuse the common pinctrl-mvebu.c logic. Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-by: Shadi Ammouri <shadi@marvell.com> [updated for mvebu pinctrl and 4.9 changes: - converted to simple_mmio - converted to syscon/regmap - removed unimplemented .remove function - dropped DTS changes - defered gpio ranges to DT - fixed warning - properly set soc->nmodes -- rmk] Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> [ add missing MPP[61:56] function 14 (SDIO) -- Konstantin Porotchkin] Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [ allow to properly register more then one instance of this driver -- Grzegorz Jaszczyk] Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> [ - rebased on 4.12-rc1 - fixed the 80 character limit for mvebu_mpp_mode array - aligned the compatible name on the ones already used - fixed the MPP table for CP110: some MPP are not available on Armada 7K -- Gregory CLEMENT] Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: mvebu: add driver for Armada AP806 pinctrlHanna Hawa2017-06-163-0/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a pinctrl driver for the pin-muxing controller found in the AP806 part of the Marvell Armada 7K and 8K SoCs. Its register interface is compatible with the one used by previous mvebu pin controllers, so the common logic in drivers/pinctrl/mvebu/pinctrl-mvebu.c is used. Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-by: Shadi Ammouri <shadi@marvell.com> [updated for mvebu pinctrl changes - converted to simple_mmio - removed unimplemented .remove function - removed DTS description - converted to use syscon/regmap --rmk] Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: avoid PLAT_ORION dependencyRussell King2017-06-161-4/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Armada 8040 also needs orion pinctrl, and as these symbols are only selected, there's no need to make them depend on PLAT_ORION. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: mvebu: remove the offset property for regmapGregory CLEMENT2017-06-162-6/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The offset property of the pinctrl node, when a regmap is used in the device tree, was never used nor documented in the binding. Moreover, the compatible string is enough to let the driver know which offset using. So this patch removes the property and move the information at the driver level. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: meson-gxl: add tsin_a pinsJerome Brunet2017-06-161-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Tsin A pins to bank DV and X. We don't have a driver for the tsin yet but since the tsin A pinmux is enabled by default at boot time, declaring this pinmux is required to properly operate on GPIOX. Without this change, GPIOX 8, 9, 10 and 11 can't be driven as GPIO output as the tsin A seems to have priority. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: intel: Add Intel Cannon Lake PCH pin controller supportMika Westerberg2017-06-093-0/+451
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds pinctrl/GPIO support for Intel Cannon Lake PCH. The Cannon Lake PCH GPIO is based on newer version of the Intel GPIO hardware. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: intel: Make it possible to specify mode per pin in a groupMika Westerberg2017-06-092-8/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some SoCs not all pins in a group use the same mode when a certain function is muxed out of them. This makes it possible to specify mode per pin as an array instead in addition to single integer. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: intel: Add support for variable size pad groupsMika Westerberg2017-06-093-56/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Intel GPIO hardware has a concept of pad groups, which means 1 to 32 pads occupying their own GPI_IS, GPI_IE, PAD_OWN and so on registers. The existing hardware has the same amount of pads in each pad group (except the last one) so it is possible to use community->gpp_size to calculate start offset of each register. With the next generation SoCs the pad group size is not always the same anymore which means we cannot use community->gpp_size for register offset calculations directly. To support variable size pad groups we introduce struct intel_padgroup that can be filled in by the client drivers according the hardware pad group layout. The core driver will always use these when it performs calculations for pad register offsets. The core driver will automatically populate pad groups based on community->gpp_size if the driver does not provide any. This makes sure the existing drivers still work as expected. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Chuah, Kim Tatt <kim.tatt.chuah@intel.com> Signed-off-by: Tan Jui Nee <jui.nee.tan@intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: sunxi: Add support for A83T R_PIOChen-Yu Tsai2017-06-093-0/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The R_PIO on the A83T is almost the same as the one found on the A64, except that the CIR_RX function was moved from pin PL11 to pin PL12. Add a driver for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: bcm: cleanup Broadcom license headersScott Branden2017-06-094-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use consistent license headers for Broadcom files by placing additional comments outside of standard legal header. Also, update legal header to 2017 format as "Broadcom Corporation" has changed to "Broadcom". Signed-off-by: Scott Branden <scott.branden@broadcom.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: sunxi: constify irq_domain_opsTobias Klauser2017-06-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | struct irq_domain_ops is not modified, so it can be made const. Suggested-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Tobias Klauser <tklauser@distanz.ch> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: stm32: remove useless checkAlexandre TORGUE2017-06-091-5/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no link between the number of elements of tab which contains all pin desc (located in each pinctrl-stm32xxxx.c files) and the pin number (defined in the tab). Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | pinctrl: meson: add interrupts to pinctrl dataJerome Brunet2017-06-095-46/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add GPIO interrupt information to pinctrl data. Added to the original version from Jerome was data for Meson GXL. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-12 11:40:47 +0200