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* | | pinctrl: stm32: constify gpio_chip structuresJulia Lawall2016-09-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These structures are only used to copy into other structures, so declare them as const. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct gpio_chip i@p = { ... }; @ok@ identifier r.i; expression e; position p; @@ e = i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct gpio_chip e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct gpio_chip i = { ... }; // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl/amd: switch to using a bool for levelAgrawal, Nitesh-kumar2016-09-131-5/+4Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The earlier patch can be simplified by using a bool to indicate level trigger. Reviewed-by: Pankaj Sen <Pankaj.Sen@amd.com> Signed-off-by: Nitesh Kumar Agrawal <Nitesh-kumar.Agrawal@amd.com> [Fixup to earlier manually applied patch] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: Add IRQ support to STM32 gpiosAlexandre TORGUE2016-09-132-1/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds IRQ support to STM32 gpios. The EXTI controller has 16 lines dedicated to GPIOs. EXTI line n can be connected to only line n of one of the GPIO ports, for example EXTI0 can be connected to either PA0, or PB0, or PC0... This port selection is done by specifying the port number into System Config registers. Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: imx: accept gpio request/free from pinctrlVladimir Zapolskiy2016-09-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While only Freescale Vybrid SoC has settings of GPIO capabilities done by iomux controller, it is only a matter of GPIO controller driver implementation for the rest of Freescale/NXP SoCs from iMX series. As a practical example on GPIO request a pad function should be switched to GPIO, but because this requires updates to all particular iMX pinctrl drivers, for simplicity at the moment add only a proper connection between shared pinctrl-imx and pinctrl/pinmux core, namely .gpio_request_enable/.gpio_disable_free/.gpio_set_direction callbacks should return success to a caller. This change allows to progress by adding request/free callbacks into gpio-mxc.c driver. Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl/at91: Don't provide a default trigger typeMarc Zyngier2016-09-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | at91 used to set a default trigger type for GPIO interrupts in order to cope with the old board files. These days are long gone, and it all gets probed through DT. Andras Szemzo reported that the Ethernet device on his board was bailing to be probed, due to a conflict in interrupt trigger. Surely enough, this is due to this default trigger still being present, and turning this into a IRQ_TYPE_NONE fixes the issue. Reported-by: Andras Szemzo <szemzo.andras@gmail.com> Tested-by: Andras Szemzo <szemzo.andras@gmail.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: sunxi: Remove unsupported PWM channel pinmux in H3Milo Kim2016-09-081-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | H3 has single PWM channel. The second PWM channel is not supported, so the pinctrl function should be removed. Signed-off-by: Milo Kim <woogyom.kim@gmail.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: bcm281xx: constify pinctrl_ops and pinmux_ops structuresJulia Lawall2016-09-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check for pinctrl_ops and pinmux_ops structures that are only stored in the pctlops field and the pmxops field, respectively, of a pinctrl_desc structure. These fields are declared const, so pinctrl_ops and pinmux_ops structures that have this property can be declared as const also. The semantic patch that makes this change in the pinctrl_ops is as follows. The pinmux_ops case is similar. (http://coccinelle.lip6.fr/) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct pinctrl_ops i@p = { ... }; @ok@ identifier r.i; struct pinctrl_desc e; position p; @@ e.pctlops = &i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct pinctrl_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct pinctrl_ops i = { ... }; // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: nsp: constify pinctrl_ops and pinmux_ops structuresJulia Lawall2016-09-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check for pinctrl_ops and pinmux_ops structures that are only stored in the pctlops field and the pmxops field, respectively, of a pinctrl_desc structure. These fields are declared const, so pinctrl_ops and pinmux_ops structures that have this property can be declared as const also. The semantic patch that makes this change in the pinctrl_ops is as follows. The pinmux_ops case is similar. (http://coccinelle.lip6.fr/) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct pinctrl_ops i@p = { ... }; @ok@ identifier r.i; struct pinctrl_desc e; position p; @@ e.pctlops = &i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct pinctrl_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct pinctrl_ops i = { ... }; // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: ns2: constify pinctrl_ops and pinmux_ops structuresJulia Lawall2016-09-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check for pinctrl_ops and pinmux_ops structures that are only stored in the pctlops field and the pmxops field, respectively, of a pinctrl_desc structure. These fields are declared const, so pinctrl_ops and pinmux_ops structures that have this property can be declared as const also. The semantic patch that makes this change in the pinctrl_ops is as follows. The pinmux_ops case is similar. (http://coccinelle.lip6.fr/) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct pinctrl_ops i@p = { ... }; @ok@ identifier r.i; struct pinctrl_desc e; position p; @@ e.pctlops = &i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct pinctrl_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct pinctrl_ops i = { ... }; // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl/amd: Configure GPIO register using BIOS settingsAgrawal, Nitesh-kumar2016-09-071-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the function amd_gpio_irq_set_type, use the settings provided by the BIOS,when the LevelTrig is Edge and activeLevel is HIGH, to configure the GPIO registers. Ignore the settings from client. Reviewed-by: Pankaj Sen <Pankaj.Sen@amd.com> Signed-off-by:Nitesh Kumar Agrawal <Nitesh-kumar.Agrawal@amd.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: sunxi: Add GR8 controller supportMylène Josserand2016-09-073-0/+546
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just like the other member of the sunxi family, let's add a pinctrl table for the muxing options. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: Add pinctrl-aspeed-g5 driverAndrew Jeffery2016-09-073-0/+817
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: Add pinctrl-aspeed-g4 driverAndrew Jeffery2016-09-073-0/+1240
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A subset of the pins and functions are exposed. The selection of functions and pins is driven by the development of OpenBMC[1] on the AST2400 SoC, particularly around booting the OpenPOWER Palmetto development machine. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: Add core support for Aspeed SoCsAndrew Jeffery2016-09-076-0/+1081
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Aspeed SoCs typically provide more than 200 pins for GPIO and other functions. The signal enabled on a pin is determined on a priority basis, where a given pin can provide a number of different signal types. In addition to the priority levels, the Aspeed pin controllers describe the signal active on a pin by compound logical expressions involving multiple operators, registers and bits. Some difficulty arises as a pin's function bit masks for each priority level are frequently not the same (i.e. we cannot just flip a bit to change from a high to low priority signal), or even in the same register(s). Some configuration bits affect multiple pins, while in other cases the signals for a bus must each be enabled individually. Together, these features give rise to some complexity in the implementation. A more complete description of the complexities is provided in the associated header file. The patch doesn't implement pinctrl/pinmux/pinconf for any particular Aspeed SoC, rather it adds the framework for defining pinmux configurations. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: meson-gxbb: add the pins for the SDIO/sd_emmc_a controllerMartin Blumenstingl2016-09-071-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | sd_emmc_a is used a controller for the SDIO modules. This adds the pin configuration for the SDIO controller. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: zynq: fix typo in sdio1_3_grp pin listDaniel Glöckner2016-09-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | It contains pin 50 instead of pin 40. Signed-off-by: Daniel Glöckner <dg@emlix.com> Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | Merge tag 'sh-pfc-for-v4.9-tag2' of ↵Linus Walleij2016-09-065-0/+2660
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Add support for R-Car M3-W Add initial support for the Pin Function Controller on the Renesas R-Car M3-W SoC: - Basic definitions, - SCIF (serial) pins, groups and functions, - SDHI pins, groups and functions.
| * | pinctrl: sh-pfc: r8a7796: Add SDHI pins, groups and functionsTakeshi Kihara2016-08-191-0/+275
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds SDHI pins, groups and functions to R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7796: Add SCIF pins, groups and functionsTakeshi Kihara2016-08-191-0/+300
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds SCIF{0,1,2,3,4,5} pins, groups and functions to R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: Initial R8A7796 PFC supportTakeshi Kihara2016-08-195-0/+2085
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds initial pinctrl driver to support for the R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [uli: rebased on top of renesas-drivers] Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | | pinctrl: imx: output one pin/config pair per line in pinconf-groupsVladimir Zapolskiy2016-09-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cat /sys/kernel/debug/pinctrl/${pinctrl}/pinconf-groups output is hardly readable, if a pin group contains more than one pin the output is glued and looks like this: MX6Q_PAD_SD1_DAT0: 0x17071MX6Q_PAD_SD1_CMD: 0x17071MX6Q_PAD_SD1_CLK: 0x17071 Add two space indentation and a new line separator to improve readability of the output. Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: sirf: make core support explicitly non-modularPaul Gortmaker2016-08-271-7/+5Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Makefile currently controlling compilation of this code is: drivers/pinctrl/sirf/pinctrl-sirf.o --> drivers/pinctrl/sirf/Makefile:obj-y += pinctrl-sirf.o ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Rongjun Ying <rongjun.ying@csr.com> Cc: Yuping Luo <yuping.luo@csr.com> Cc: Barry Song <baohua@kernel.org> Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: sirf: make atlas7 explicitly non-modularPaul Gortmaker2016-08-271-4/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Makefile currently controlling compilation of this code is: drivers/pinctrl/sirf/pinctrl-atlas7.o ---> drivers/pinctrl/sirf/Makefile:obj-y += pinctrl-atlas7.o ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. We delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Barry Song <baohua@kernel.org> Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: rockchip: make it explicitly non-modularPaul Gortmaker2016-08-271-6/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig currently controlling compilation of this code is: drivers/pinctrl/Kconfig:config PINCTRL_ROCKCHIP drivers/pinctrl/Kconfig: bool ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. Note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: linux-gpio@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: nomadik: make core support explicitly non-modularPaul Gortmaker2016-08-271-5/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig currently controlling compilation of this code is: drivers/pinctrl/nomadik/Kconfig:config PINCTRL_NOMADIK drivers/pinctrl/nomadik/Kconfig: bool "Nomadik pin controller driver" ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. We delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Alessandro Rubini <rubini@unipv.it> Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: nomadik: make abx500 explicitly non-modularPaul Gortmaker2016-08-271-6/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig currently controlling compilation of this code is: config PINCTRL_ABX500 bool "ST-Ericsson ABx500 family Mixed Signal Circuit gpio functions" ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. Note that MODULE_ALIAS is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Alessandro Rubini <rubini@unipv.it> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: mediatek: make mtk-common explicitly non-modularPaul Gortmaker2016-08-271-5/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Makefile currently controlling compilation of this code is: drivers/pinctrl/mediatek/pinctrl-mtk-common.o ---> drivers/pinctrl/mediatek/Makefile:obj-y += pinctrl-mtk-common.o ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. We delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. We don't replace module.h with init.h since the file doesn't need that. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Hongzhou Yang <hongzhou.yang@mediatek.com> Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: meson-gxbb: add pins for PWMNeil Armstrong2016-08-241-0/+79
| | | | | | | | | | | | | | | | | | | | | Add support for PWM pins, for EE and AO domains. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | Merge tag 'sh-pfc-for-v4.9-tag1' of ↵Linus Walleij2016-08-226-53/+3047
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.9 - Bias and DU support for R-Car H3, - Basic R-Car V2H support, - Cleanups and fixes.
| * | pinctrl: sh-pfc: r8a7795: Add DU supportLaurent Pinchart2016-08-161-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | Only the DU parallel RGB output signals are included, HDMI and TCON pins will be added in separate groups. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7792: Add DU pin groupsSergei Shtylyov2016-08-081-0/+144
| | | | | | | | | | | | | | | | | | | | | Add DU pin groups to the R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7792: Add VIN pin groupsSergei Shtylyov2016-08-081-0/+577
| | | | | | | | | | | | | | | | | | | | | | | | Add VIN[0-5] pin groups to the R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> [geert: Fix VI1_D14_G6_Y6 and VI1_D15_G7_Y7 pins] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7795: Correct header from R-Car Gen3 to R8A7795Geert Uytterhoeven2016-08-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This source file handles r8a7795 only, which is not the sole member of the R-Car Gen3 family. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sh-pfc: r8a7792: Add CAN pin groupsSergei Shtylyov2016-08-081-0/+37
| | | | | | | | | | | | | | | | | | | | | Add CAN0/1 data/clock pin groups to R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7792: Add SDHI pin groupsSergei Shtylyov2016-08-081-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | Add SDHI0 pin groups to the R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7792: Add EtherAVB pin groupsSergei Shtylyov2016-08-081-0/+99
| | | | | | | | | | | | | | | | | | | | | Add the EtherAVB pin groups to the R8A7792 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: Add R8A7792 PFC supportSergei Shtylyov2016-08-085-6/+1747
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the PFC support for the R8A7792 SoC including pin groups for some on-chip devices such as SCIF, INTC, and LBSC... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> [geert: s/LSBC/LBSC/] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: Fix overly long linesSergei Shtylyov2016-08-081-40/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | The PORT_GP_CFG_<n>() macros take up more than 80 columns -- and not for a good reason. Make the header file checkpatch.pl-proof at least in this respect... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7795: Add bias pinconf supportUlrich Hecht2016-08-081-12/+242
| |/ | | | | | | | | | | | | | | Implements pull-up and pull-down. On this SoC there is no simple mapping of GP pins to bias register bits, so we need a table. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | pinctrl: amlogic: gxbb: add the IR remote input pinMartin Blumenstingl2016-08-221-0/+8
| | | | | | | | | | | | | | | | This adds the IR remote receiver to the AO domain devices. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: palmas: fix a possible NULL dereferenceLABBE Corentin2016-08-221-3/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | of_match_device could return NULL, and so cause a NULL pointer dereference later at line 1009: pinctrl_data = match->data; For fixing this problem, we use of_device_get_match_data(), this will simplify the code a little by using a standard function for getting the match data. Reported-by: coverity (CID 1324136) Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: exynos: remove duplicate calls in irq handlerperr perr2016-08-221-5/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | Because chained_irq_enter() has already called chip->irq_mask() and chip->irq_ack(), also chained_irq_exit() will call chip->irq_unmask(), so it's not necessary to call chip->irq_*() here. Signed-off-by: Perr Zhang <strongbox8@zoho.com> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> [Hand-edited from whitespace damaged patch] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: meson: get rid of unneeded domain structuresBeniamino Galvani2016-08-225-228/+118Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver originally supported more domains (register ranges) per pinctrl device, but since commit 9dab1868ec0d ("pinctrl: amlogic: Make driver independent from two-domain configuration") each device gets assigned a single domain and we instantiate multiple pinctrl devices in the DT. Therefore, now the 'meson_domain' and 'meson_domain_data' structures don't have any reason to exist and can be removed to make the model simpler to understand. This commit doesn't change behavior. Tested on a Odroid-C2. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: st: Use second parameter to gpio specifierPatrice Chotard2016-08-111-17/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows to use the second parameter of gpio specifier, which is used to specify whether the gpio is active high or low. Simply remove specific of_xlate callback() and of_gpio_n_cells and use default one set by of_gpiochip_add() which allows to use second parameter gpio specifier. Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: nomadik: use of_property_read_boolJulia Lawall2016-08-111-4/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use of_property_read_bool to check for the existence of a property. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression e1,e2,x; @@ - if (of_get_property(e1,e2,NULL)) - x = true; - else - x = false; + x = of_property_read_bool(e1,e2); // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: qcom: Add generic ssbi and spmi GPIO/MPP bindingsStephen Boyd2016-08-112-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The drivers don't really need to know which PMIC they're for, so make a generic binding for them. This alleviates us from updating the drivers every time a new PMIC comes out. It's still recommended that we update the binding with new PMIC models and always specify the specific model for the MPPs and gpios before the generic compatible string in devicetree, but this at least cuts down on adding more and more compatible strings to the drivers until we actually need them. Cc: <devicetree@vger.kernel.org> Acked-by: "Ivan T. Ivanov" <iivanov.xz@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: sun6i: add SPDIF to pin description.Marcus Cooper2016-08-111-2/+10
|/ | | | | | | | | Add the SPDIF mux functionality to the pinctrl for the Allwinner A31 SoC. Signed-off-by: Marcus Cooper <codekipper@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v4.8-1' of ↵Linus Torvalds2016-07-29105-2681/+10726
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.8 kernel cycle. Nothing stands out as especially exiting: new drivers, new subdrivers, lots of cleanups and incremental features. Business as usual. New drivers: - New driver for Oxnas pin control and GPIO. This ARM-based chipset is used in a few storage (NAS) type devices. - New driver for the MAX77620/MAX20024 pin controller portions. - New driver for the Intel Merrifield pin controller. New subdrivers: - New subdriver for the Qualcomm MDM9615 - New subdriver for the STM32F746 MCU - New subdriver for the Broadcom NSP SoC. Cleanups: - Demodularization of bool compiled-in drivers. Apart from this there is just regular incremental improvements to a lot of drivers, especially Uniphier and PFC" * tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (131 commits) pinctrl: fix pincontrol definition for marvell pinctrl: xway: fix typo Revert "pinctrl: amd: make it explicitly non-modular" pinctrl: iproc: Add NSP and Stingray GPIO support pinctrl: Update iProc GPIO DT bindings pinctrl: bcm: add OF dependencies pinctrl: ns2: remove redundant dev_err call in ns2_pinmux_probe() pinctrl: Add STM32F746 MCU support pinctrl: intel: Protect set wake flow by spin lock pinctrl: nsp: remove redundant dev_err call in nsp_pinmux_probe() pinctrl: uniphier: add Ethernet pin-mux settings sh-pfc: Use PTR_ERR_OR_ZERO() to simplify the code pinctrl: ns2: fix return value check in ns2_pinmux_probe() pinctrl: qcom: update DT bindings with ebi2 groups pinctrl: qcom: establish proper EBI2 pin groups pinctrl: imx21: Remove the MODULE_DEVICE_TABLE() macro Documentation: dt: Add new compatible to STM32 pinctrl driver bindings includes: dt-bindings: Add STM32F746 pinctrl DT bindings pinctrl: sunxi: fix nand0 function name for sun8i pinctrl: uniphier: remove pointless pin-mux settings for PH1-LD11 ...
| * pinctrl: fix pincontrol definition for marvellAndreas Klinger2016-07-241-42/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Marvell mv88f6180 with pin control driver one can not use multi purpose pins 35 through 44. I'm using this controller on an embedded board and i found that the pin multiplexing is not the same as in the hardware spezification. This patch alters the pin description so that mpp pins 0 to 19 as well as 35 to 44 are usable. Pin settings i used can be found here: http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6180_OpenSource.pdf Signed-off-by: Andreas Klinger <ak@it-klinger.de> Reviewed-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: xway: fix typoLinus Walleij2016-07-221-1/+1
| | | | | | | | | | | | | | | | | | A typo in the previous commit to this file needs fixing. Cc: Amitoj Kaur Chawla <amitoj1606@gmail.com> Reported-by: kbuild test robot <fengguang.wu@intel.com> Fixes: 6b4316aecec0 ("pinctrl: xway: Change structure initialisation to c99 style") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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