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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Olof Johansson:
"Some of the larger changes this merge window:
- Removal of drivers for Exynos5440, a Samsung SoC that never saw
widespread use.
- Uniphier support for USB3 and SPI reset handling
- Syste control and SRAM drivers and bindings for Allwinner platforms
- Qualcomm AOSS (Always-on subsystem) reset controller drivers
- Raspberry Pi hwmon driver for voltage
- Mediatek pwrap (pmic) support for MT6797 SoC"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (52 commits)
drivers/firmware: psci_checker: stash and use topology_core_cpumask for hotplug tests
soc: fsl: cleanup Kconfig menu
soc: fsl: dpio: Convert DPIO documentation to .rst
staging: fsl-mc: Remove remaining files
staging: fsl-mc: Move DPIO from staging to drivers/soc/fsl
staging: fsl-dpaa2: eth: move generic FD defines to DPIO
soc: fsl: qe: gpio: Add qe_gpio_set_multiple
usb: host: exynos: Remove support for Exynos5440
clk: samsung: Remove support for Exynos5440
soc: sunxi: Add the A13, A23 and H3 system control compatibles
reset: uniphier: add reset control support for SPI
cpufreq: exynos: Remove support for Exynos5440
ata: ahci-platform: Remove support for Exynos5440
soc: imx6qp: Use GENPD_FLAG_ALWAYS_ON for PU errata
soc: mediatek: pwrap: add mt6351 driver for mt6797 SoCs
soc: mediatek: pwrap: add pwrap driver for mt6797 SoCs
soc: mediatek: pwrap: fix cipher init setting error
dt-bindings: pwrap: mediatek: add pwrap support for MT6797
reset: uniphier: add USB3 core reset control
dt-bindings: reset: uniphier: add USB3 core reset support
...
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https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/drivers
Exynos5440 drivers removal
The Exynos5440 (quad-core A15 with GMAC, PCIe, SATA) was targeting
server platforms but it did not make it to the market really. There are
no development boards with it and probably there are no real products
neither. The development for Exynos5440 ended in 2013 and since then
the platform is in maintenance mode.
Removing Exynos5440 makes our life slightly easier: less maintenance,
smaller code, reduced number of quirks, no need to preserve DTB
backward-compatibility.
The Device Tree sources and some of the drivers for Exynos5440 were
already removed. This removes remaining drivers.
* tag 'samsung-drivers-exynos5440-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
usb: host: exynos: Remove support for Exynos5440
clk: samsung: Remove support for Exynos5440
cpufreq: exynos: Remove support for Exynos5440
ata: ahci-platform: Remove support for Exynos5440
Signed-off-by: Olof Johansson <olof@lixom.net>
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The Exynos5440 is not actively developed, there are no development
boards available and probably there are no real products with it.
Remove wide-tree support for Exynos5440.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Sylwester Nawrocki <snawrocki@kernel.org>
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Add clkctrl data for the m_can clocks and register it within the
clkctrl driver
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
CC: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"The new and exciting feature this time around is in the clk core.
We've added duty cycle support to the clk API so that clk signal duty
cycle ratios can be adjusted while taking into account things like clk
dividers and clk tree hierarchy. So far only one SoC has implemented
support for this, but I expect there will be more to come in the
future.
Outside of the core, we have the usual pile of clk driver updates and
additions. The Amlogic meson driver got the most lines in the diffstat
this time around because it added support for a whole bunch of
hardware and duty cycle configuration. After that the Rockchip PX30,
Qualcomm SDM845, and Renesas SoC drivers fill in a majority of the
diff. We're left with the collection of non-critical fixes after that.
Overall it looks pretty quiet this time.
Core:
- Clk duty cycle support
- Proper CLK_SET_RATE_GATE support throughout the tree
New Drivers:
- Actions Semi Owl series S700 SoC clk driver
- Qualcomm SDM845 display clock controller
- i.MX6SX ocram_s clk support
- Uniphier NAND, USB3 PHY, and SPI clk support
- Qualcomm RPMh clk driver
- i.MX7D mailbox clk support
- Maxim 9485 Programmable Clock Generator
- expose 32 kHz PLL on PXA SoCs
- imx6sll GPIO clk gate support
- Atmel at91 I2S audio clk support
- SI544/SI514 clk on/off support
- i.MX6UL GPIO clock gates in CCM CCGR
- Renesas Crypto Engine clocks on R-Car H3
- Renesas clk support for the new RZ/N1D SoC
- Allwinner A64 display engine clock support
- support for Rockchip's PX30 SoC
- Amlogic Meson axg PCIe and audio clocks
- Amlogic Meson GEN CLK on gxbb, gxl and axg
Updates:
- remove an unused variable from Exynos4412 ISP driver
- fix a thinko bug in SCMI clk division logic
- add missing of_node_put()s in some i.MX clk drivers
- Tegra SDMMC clk jitter improvements with high speed signaling modes
- SPDX tagging for qcom and cs2000-cp drivers
- stop leaking con ids in __clk_put()
- fix a corner case in fixed factor clk probing where node is in DT
but parent clk is registered much later
- Marvell Armada 3700 clk_pm_cpu_get_parent() had an invalid return
value
- i.MX clk init arrays removed in place of CLK_IS_CRITICAL
- convert to CLK_IS_CRITICAL for i.MX51/53 driver
- fix Tegra BPMP driver oops when xlating a NULL clk
- proper default configuration for vic03 and vde clks on Tegra124
- mark Tegra memory controller clks as critical
- fix array bounds clamp in Tegra's emc determine_rate() op
- Ingenic i2s bit update and allow UDC clk to gate
- fix name of aspeed SDC clk define to have only one 'CLK'
- fix i.MX6QDL video clk parent
- critical clk markings for qcom SDM845
- fix Stratix10 mpu_free_clk and sdmmc_free_clk parents
- mark Rockchip's pclk_rkpwm_pmu as critical clock, due to it
supplying the pwm used to drive the logic supply of the rk3399
core"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (85 commits)
clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399
clk: cs2000-cp: convert to SPDX identifiers
clk: scmi: Fix the rounding of clock rate
clk: qcom: Add display clock controller driver for SDM845
clk: mvebu: armada-37xx-periph: Remove unused var num_parents
clk: samsung: Remove unused mout_user_aclk400_mcuisp_p4x12 variable
clk: actions: Add S700 SoC clock support
dt-bindings: clock: Add S700 support for Actions Semi Soc's
clk: actions: Add missing REGMAP_MMIO dependency
clk: uniphier: add clock frequency support for SPI
clk: uniphier: add more USB3 PHY clocks
clk: uniphier: add NAND 200MHz clock
clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks
clk: tegra: Add sdmmc mux divider clock
clk: tegra: Refactor fractional divider calculation
clk: tegra: Fix includes required by fence_udelay()
clk: imx6sll: fix missing of_node_put()
clk: imx6ul: fix missing of_node_put()
clk: imx: add ocram_s clock for i.mx6sx
clk: mvebu: armada-37xx-periph: Fix wrong return value in get_parent
...
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'clk-qcom-dispcc-845', 'clk-scmi-round' and 'clk-cs2000-spdx' into clk-next
* clk-actions-s700:
: - Actions Semi Owl series S700 SoC clk driver
clk: actions: Add S700 SoC clock support
dt-bindings: clock: Add S700 support for Actions Semi Soc's
clk: actions: Add missing REGMAP_MMIO dependency
* clk-exynos-unused:
: - Remove an unused variable from Exynos4412 ISP driver
clk: samsung: Remove unused mout_user_aclk400_mcuisp_p4x12 variable
* clk-qcom-dispcc-845:
: - Qualcomm SDM845 display clock controller
clk: qcom: Add display clock controller driver for SDM845
dt-bindings: clock: Introduce QCOM Display clock bindings
clk: qcom: Move frequency table macro to common file
* clk-scmi-round:
: - Fix a thinko bug in SCMI clk division logic
clk: scmi: Fix the rounding of clock rate
* clk-cs2000-spdx:
clk: cs2000-cp: convert to SPDX identifiers
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Add device tree bindings for display clock controller for Qualcomm
Technology Inc's SDM845 SoCs.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Add clock bindings constants for action S700
Maintain common clock dt-bindings for Actions Semi SoC's
S700 and S900.
Signed-off-by: Parthiban Nallathambi <pn@denx.de>
Signed-off-by: Saravanan Sekar <sravanhome@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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'clk-tegra-sdmmc-jitter', 'clk-allwinner' and 'clk-uniphier' into clk-next
* clk-imx6-ocram:
: - i.MX6SX ocram_s clk support
clk: imx: add ocram_s clock for i.mx6sx
* clk-missing-put:
: - Add missing of_node_put()s in some i.MX clk drivers
clk: imx6sll: fix missing of_node_put()
clk: imx6ul: fix missing of_node_put()
* clk-tegra-sdmmc-jitter:
: - Tegra SDMMC clk jitter improvements with high speed signaling modes
clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks
clk: tegra: Add sdmmc mux divider clock
clk: tegra: Refactor fractional divider calculation
clk: tegra: Fix includes required by fence_udelay()
* clk-allwinner:
clk: sunxi-ng: add A64 compatible string
dt-bindings: add compatible string for the A64 DE2 CCU
clk: sunxi-ng: r40: Export video PLLs
clk: sunxi-ng: r40: Allow setting parent rate to display related clocks
clk: sunxi-ng: r40: Add minimal rate for video PLLs
* clk-uniphier:
: - Uniphier NAND, USB3 PHY, and SPI clk support
clk: uniphier: add clock frequency support for SPI
clk: uniphier: add more USB3 PHY clocks
clk: uniphier: add NAND 200MHz clock
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Video PLLs need to be referenced in R40 DT as possible HDMI PHY parent.
Export them.
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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'clk-imx-init-array-cleanup' and 'clk-rockchip' into clk-next
* clk-mvebu-spdx:
clk: mvebu: armada-37xx-periph: switch to SPDX license identifier
* clk-meson:
clk: meson: add gen_clk
clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition
clk: meson-axg: add clocks required by pcie driver
clk: meson: remove unused clk-audio-divider driver
clk: meson: stop rate propagation for audio clocks
clk: meson: axg: add the audio clock controller driver
clk: meson: add axg audio sclk divider driver
clk: meson: add triple phase clock driver
clk: meson: add clk-phase clock driver
clk: meson: clean-up meson clock configuration
clk: meson: remove obsolete register access
clk: meson: expose GEN_CLK clkid
clk: meson-axg: add pcie and mipi clock bindings
dt-bindings: clock: add meson axg audio clock controller bindings
clk: meson: audio-divider is one based
clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL
* clk-imx7d-mu:
: - i.MX7D mailbox clk support
clk: imx7d: add IMX7D_MU_ROOT_CLK
* clk-imx-init-array-cleanup:
: - i.MX clk init arrays removed in place of CLK_IS_CRITICAL
clk: imx6sx: remove clks_init_on array
clk: imx6sl: remove clks_init_on array
clk: imx6q: remove clks_init_on array
* clk-rockchip:
clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399
clk: rockchip: fix clk_i2sout parent selection bits on rk3399
clk: rockchip: add clock controller for px30
clk: rockchip: add support for half divider
dt-bindings: add bindings for px30 clock controller
clk: rockchip: add dt-binding header for px30
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Add the dt-bindings header for the px30, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for px30.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Expose GEN_CLK clock id
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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Add the pcie and mipi clock dt-bindings for the pcie driver.
Since the mipi clock isalso used by the pcie driver,
we add it together in this patch.
Tested-by: Jianxin Qin <jianxin.qin@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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Export the clock ids dt-bindings usable by the consumers of the clock
controller and add the documentation for the device tree bindings of
the audio clock controller of the A113 based SoCs.
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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'clk-aspeed' and 'clk-imx6sll-gpio' into clk-next
* clk-ingenic-fixes:
: - Ingenic i2s bit update and allow UDC clk to gate
clk: ingenic: Add missing flag for UDC clock
clk: ingenic: Fix incorrect data for the i2s clock
* clk-max9485:
: - Maxim 9485 Programmable Clock Generator
clk: Add driver for MAX9485
dts: clk: add devicetree bindings for MAX9485
* clk-pxa-32k-pll:
: - Expose 32 kHz PLL on PXA SoCs
clk: pxa: export 32kHz PLL
* clk-aspeed:
: - Fix name of aspeed SDC clk define to have only one 'CLK'
clk: aspeed: Fix SDCLK name
* clk-imx6sll-gpio:
: - imx6sll GPIO clk gate support
clk: imx6sll: add GPIO LPCGs
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According to Reference Manual Rev.0, 06/2017, there are GPIO LPCGs
defined in CCM CCGRs, add them into clock tree.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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The SDCLK was named SDCLKCLK, and no one has used this yet.
Fix it.
Signed-off-by: Lei YU <mine260309@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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This clock is especially used by the RTC driver, so export it so that
devicetree users can use it.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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This patch adds the devicetree bindings for MAX9485, a programmable audio
clock generator.
Signed-off-by: Daniel Mack <daniel@zonque.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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'clk-renesas', 'clk-stratix10-fixes' and 'clk-atmel-i2s' into clk-next
* clk-imx6-video-parent:
: - Fix i.MX6QDL video clk parent
clk: imx6: fix video_27m parent for IMX6QDL_CLK_CKO1_SEL
* clk-qcom-sdm845-criticals:
: - critical clk markings for qcom SDM845
clk: qcom: Enable clocks which needs to be always on for SDM845
* clk-renesas:
clk: renesas: Renesas R9A06G032 clock driver
dt-bindings: clock: renesas,r9a06g032-sysctrl: documentation
dt-bindings: clock: Add the r9a06g032-sysctrl.h file
clk: renesas: r8a7795: Add CCREE clock
clk: renesas: r8a7795: Add CR clock
* clk-stratix10-fixes:
: - Fix Stratix10 mpu_free_clk and sdmmc_free_clk parents
clk: socfpga: stratix10: fix the sdmmc_free_clk mux
clk: socfpga: stratix10: fix the parents of mpu_free_clk
* clk-atmel-i2s:
: - Atmel at91 I2S audio clk support
clk: at91: add I2S clock mux driver
dt-bindings: clk: at91: add an I2S mux clock
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This adds the constants necessary to use the renesas,r9a06g032-sysctrl node.
Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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There are certain clocks which needs to be always enabled for system
operation. Add support for the same by adding 'CLK_IS_CRITICAL' flag
for such clocks.
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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i.MX6UL has GPIO clock gates in CCM CCGR,
add them into clock tree for clock management.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Pull drm updates from Dave Airlie:
"This is the main drm pull request for 4.19.
Rob has some new hardware support for new qualcomm hw that I'll send
along separately. This has the display part of it, the remaining pull
is for the acceleration engine.
This also contains a wound-wait/wait-die mutex rework, Peter has acked
it for merging via my tree.
Otherwise mostly the usual level of activity. Summary:
core:
- Wound-wait/wait-die mutex rework
- Add writeback connector type
- Add "content type" property for HDMI
- Move GEM bo to drm_framebuffer
- Initial gpu scheduler documentation
- GPU scheduler fixes for dying processes
- Console deferred fbcon takeover support
- Displayport support for CEC tunneling over AUX
panel:
- otm8009a panel driver fixes
- Innolux TV123WAM and G070Y2-L01 panel driver
- Ilitek ILI9881c panel driver
- Rocktech RK070ER9427 LCD
- EDT ETM0700G0EDH6 and EDT ETM0700G0BDH6
- DLC DLC0700YZG-1
- BOE HV070WSA-100
- newhaven, nhd-4.3-480272ef-atxl LCD
- DataImage SCF0700C48GGU18
- Sharp LQ035Q7DB03
- p079zca: Refactor to support multiple panels
tinydrm:
- ILI9341 display panel
New driver:
- vkms - virtual kms driver to testing.
i915:
- Icelake:
Display enablement
DSI support
IRQ support
Powerwell support
- GPU reset fixes and improvements
- Full ppgtt support refactoring
- PSR fixes and improvements
- Execlist improvments
- GuC related fixes
amdgpu:
- Initial amdgpu documentation
- JPEG engine support on VCN
- CIK uses powerplay by default
- Move to using core PCIE functionality for gens/lanes
- DC/Powerplay interface rework
- Stutter mode support for RV
- Vega12 Powerplay updates
- GFXOFF fixes
- GPUVM fault debugging
- Vega12 GFXOFF
- DC improvements
- DC i2c/aux changes
- UVD 7.2 fixes
- Powerplay fixes for Polaris12, CZ/ST
- command submission bo_list fixes
amdkfd:
- Raven support
- Power management fixes
udl:
- Cleanups and fixes
nouveau:
- misc fixes and cleanups.
msm:
- DPU1 support display controller in sdm845
- GPU coredump support.
vmwgfx:
- Atomic modesetting validation fixes
- Support for multisample surfaces
armada:
- Atomic modesetting support completed.
exynos:
- IPPv2 fixes
- Move g2d to component framework
- Suspend/resume support cleanups
- Driver cleanups
imx:
- CSI configuration improvements
- Driver cleanups
- Use atomic suspend/resume helpers
- ipu-v3 V4L2 XRGB32/XBGR32 support
pl111:
- Add Nomadik LCDC variant
v3d:
- GPU scheduler jobs management
sun4i:
- R40 display engine support
- TCON TOP driver
mediatek:
- MT2712 SoC support
rockchip:
- vop fixes
omapdrm:
- Workaround for DRA7 errata i932
- Fix mm_list locking
mali-dp:
- Writeback implementation
PM improvements
- Internal error reporting debugfs
tilcdc:
- Single fix for deferred probing
hdlcd:
- Teardown fixes
tda998x:
- Converted to a bridge driver.
etnaviv:
- Misc fixes"
* tag 'drm-next-2018-08-15' of git://anongit.freedesktop.org/drm/drm: (1506 commits)
drm/amdgpu/sriov: give 8s for recover vram under RUNTIME
drm/scheduler: fix param documentation
drm/i2c: tda998x: correct PLL divider calculation
drm/i2c: tda998x: get rid of private fill_modes function
drm/i2c: tda998x: move mode_valid() to bridge
drm/i2c: tda998x: register bridge outside of component helper
drm/i2c: tda998x: cleanup from previous changes
drm/i2c: tda998x: allocate tda998x_priv inside tda998x_create()
drm/i2c: tda998x: convert to bridge driver
drm/scheduler: fix timeout worker setup for out of order job completions
drm/amd/display: display connected to dp-1 does not light up
drm/amd/display: update clk for various HDMI color depths
drm/amd/display: program display clock on cache match
drm/amd/display: Add NULL check for enabling dp ss
drm/amd/display: add vbios table check for enabling dp ss
drm/amd/display: Don't share clk source between DP and HDMI
drm/amd/display: Fix DP HBR2 Eye Diagram Pattern on Carrizo
drm/amd/display: Use calculated disp_clk_khz value for dce110
drm/amd/display: Implement custom degamma lut on dcn
drm/amd/display: Destroy aux_engines only once
...
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rmk requested this for armada and I think we've had a few
conflicts build up.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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git://anongit.freedesktop.org/drm/drm-misc into drm-next
drm-misc-next for 4.19:
Cross-subsystem Changes:
devicetree documentation
dt-bindings defintions for sun8i (Jernej Skrabec)
Core Changes:
Consider drivers setting DRIVER_ATOMIC as atomic (Eric Anholt)
Improvements for in-kernel clients (Noralf Trønnes)
Export and rename drm_crtc_port_mask() (Jernej Skrabec)
Driver Changes:
v3d: Add looking for GPU scheduler jobs management (Eric Anholt)
Add Ilitek ILI9881c panel driver(Maxime Ripard)
rockchip: vop: fixup linebuffer mode calc error (Sandy Huang)
tinydrm: new driver for ILI9341 display panels (David Lechner)
sun4i: Add TCON TOP driver (Jernej Skrabec)
Signed-off-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180628010018.GA10929@juma
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TCON TOP main purpose is to configure whole display pipeline. It
determines relationships between mixers and TCONs, selects source TCON
for HDMI, muxes LCD and TV encoder GPIO output, selects TV encoder
clock source and contains additional TV TCON and DSI gates.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180625120304.7543-5-jernej.skrabec@siol.net
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* clk-stm32mp1:
clk: stm32mp1: remove ck_apb_dbg clock
clk: stm32mp1: set stgen_k clock as critical
clk: stm32mp1: add missing tzc2 clock
clk: stm32mp1: fix SAI3 & SAI4 clocks
clk: stm32mp1: remove unused dfsdm_src[] const
clk: stm32mp1: add missing static
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DDR3 SDRAM Standard (JESD79-3F) defines some standard speed bins for
DDR3 memories. The rk3399_dmc driver allows you to pass these values via
the device tree. For that purpose the devfreq/rk3399_dmc.txt binding
refers to a ddr.h file which does not exist. This patch adds the missing
defines in a include file called rk3399-ddr.h with the definition of
standard speed bins according to the ARM Trusted Firmware (ATF).
Fixes: c1ceb8f7c167 (Documentation: bindings: add dt documentation for rk3399 dmc)
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
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Commit f5a4670de966 ("clk: imx: Add new clo01 and clo2 controlled
by CCOSR") introduced the CLK_CLKO definitions, but didn't put them
at the end of the list, which may cause dtb breakage when running an old
dtb with a newer kernel.
In order to avoid that, simply add the new CLK_CKO clock definitions
at the end of the list.
Fixes: f5a4670de966 ("clk: imx: Add new clo01 and clo2 controlled by CCOSR")
Reported-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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'clk-davinci' and 'clk-meson' into clk-next
* clk-davinci-psc-da830:
clk: davinci: psc-da830: fix USB0 48MHz PHY clock registration
* clk-renesas:
clk: renesas: cpg-mssr: Add support for R-Car E3
clk: renesas: Add r8a77990 CPG Core Clock Definitions
clk: renesas: rcar-gen2: Centralize quirks handling
clk: renesas: r8a77980: Correct parent clock of PCIEC0
clk: renesas: r8a7794: Fix LB clock divider
clk: renesas: r8a7792: Fix LB clock divider
clk: renesas: r8a7791/r8a7793: Fix LB clock divider
clk: renesas: r8a7745: Fix LB clock divider
clk: renesas: r8a7743: Fix LB clock divider
clk: renesas: cpg-mssr: Add r8a77470 support
clk: renesas: Add r8a77470 CPG Core Clock Definitions
clk: renesas: r8a77965: Add MSIOF controller clocks
* clk-at91-recalc:
clk: at91: PLL recalc_rate() now using cached MUL and DIV values
* clk-davinci:
clk: davinci: Fix link errors when not all SoCs are enabled
clk: davinci: psc: allow for dev == NULL
clk: davinci: da850-pll: change PLL0 to CLK_OF_DECLARE
clk: davinci: pll: allow dev == NULL
clk: davinci: psc-dm365: fix few clocks
clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled
clk: davinci: psc-dm355: fix ASP0/1 clkdev lookups
clk: davinci: pll-dm355: fix SYSCLKn parent names
clk: davinci: pll-dm355: drop pll2_sysclk2
* clk-meson:
clk: meson: axg: let mpll clocks round closest
clk: meson: mpll: add round closest support
clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICAL
clk: meson: use SPDX license identifiers consistently
clk: meson: drop CLK_SET_RATE_PARENT flag
clk: meson-axg: Add AO Clock and Reset controller driver
clk: meson: aoclk: refactor common code into dedicated file
clk: meson: migrate to devm_of_clk_add_hw_provider API
clk: meson: gxbb: add the video decoder clocks
clk: meson: meson8b: add support for the NAND clocks
dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
clk: meson: gxbb: expose VDEC_1 and VDEC_HEVC clocks
dt-bindings: clock: meson8b: export the NAND clock
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Add dt-bindings headers for the Meson-AXG's AO clock and
reset controller.
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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Export video decoder clock dt-bindings
Signed-off-by: Maxime Jourdan <maxi.jourdan@wanadoo.fr>
[added commit description]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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Export the NAND clock to the dt-bindings.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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This patch adds all R-Car E3 Clock Pulse Generator Core Clock Outputs.
Note that internal CPG clocks (S0, S1, S2, S3, SDSRC, POST3) are not
included, as they are used as internal clock sources only, and never
referenced from DT.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[shimoda: add SPDX-License-Identifier]
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add all RZ/G1C Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2 ("List of Clocks [RZ/G1C]") of the RZ/G1C Hardware User's
Manual.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
[geert: Use consecutive numbering]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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* clk-qcom-sdm845:
clk: qcom: Export clk_fabia_pll_configure()
clk: qcom: Add video clock controller driver for SDM845
dt-bindings: clock: Introduce QCOM Video clock bindings
clk: qcom: Add Global Clock controller (GCC) driver for SDM845
clk: qcom: Add DT bindings for SDM845 gcc clock controller
clk: qcom: Configure the RCGs to a safe source as needed
clk: qcom: Add support for BRANCH_HALT_SKIP flag for branch clocks
clk: qcom: Simplify gdsc status checking logic
clk: qcom: gdsc: Add support to poll CFG register to check GDSC state
clk: qcom: gdsc: Add support to poll for higher timeout value
clk: qcom: gdsc: Add support to reset AON and block reset logic
clk: qcom: Add support for controlling Fabia PLL
clk: qcom: Clear hardware clock control bit of RCG
Also fixup the Kconfig mess where SDM845 GCC has msm8998 in the
description and also the video Kconfig says things slightly differently
from the GCC one so just make it the same.
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Add device tree bindings for video clock controller for
Qualcomm Technology Inc's SoCs.
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Add compatible string and the include file for gcc clock
controller for SDM845.
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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'clk-bcm-stingray' into clk-next
* clk-match-string:
clk: use match_string() helper
clk: bcm2835: use match_string() helper
* clk-ingenic:
clk: ingenic: jz4770: Add 150us delay after enabling VPU clock
clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock
clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle
clk: ingenic: jz4770: Change OTG from custom to standard gated clock
clk: ingenic: Support specifying "wait for clock stable" delay
clk: ingenic: Add support for clocks whose gate bit is inverted
* clk-si544-round-fix:
clk-si544: Properly round requested frequency to nearest match
* clk-bcm-stingray:
clk: bcm: Update and add Stingray clock entries
dt-bindings: clk: Update Stingray binding doc
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Update Stingray clock binding document to add additional clock entries
with names matching the latest ASIC datasheet. Also modify a few existing
entries to make their naming more consistent with the rest of the entries
Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com>
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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and 'clk-debugfs-simple' into clk-next
* clk-imx7d:
clk: imx7d: reset parent for mipi csi root
clk: imx7d: fix mipi dphy div parent
* clk-hisi-stub:
clk/driver/hisi: Consolidate the Kconfig for the CLOCK_STUB
* clk-mvebu:
clk: mvebu: use correct bit for 98DX3236 NAND
* clk-imx6-epit:
clk: imx6: add EPIT clock support
* clk-debugfs-simple:
clk: Return void from debug_init op
clk: remove clk_debugfs_add_file()
clk: tegra: no need to check return value of debugfs_create functions
clk: davinci: no need to check return value of debugfs_create functions
clk: bcm2835: no need to check return value of debugfs_create functions
clk: no need to check return value of debugfs_create functions
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Add EPIT clock support to the i.MX6Q clocking infrastructure.
Signed-off-by: Colin Didier <colin.didier@devialet.com>
Signed-off-by: Clément Peron <clement.peron@devialet.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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* clk-imx6sx:
clk: imx6sl: correct ocram_podf clock type
clk: imx6sx: disable unnecessary clocks during clock initialization
clk: imx6sx: add missing lvds2 clock to the clock tree
* clk-imx7d-enet:
ARM: dts: imx7: correct enet ipg clock
clk: imx7d: correct enet clock CCGR registers
clk: imx7d: correct enet phy ref clock gates
* clk-aspeed-24:
clk: aspeed: Add 24MHz fixed clock
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Add a 24MHz fixed clock.
This clock will be used for certain devices, e.g. pwm.
Signed-off-by: Lei YU <mine260309@gmail.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Correct enet clock gates as below:
CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 and enet2 bus clocks)
CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK
CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK
Just rename unused IMX7D_ENETx_REF_ROOT_CLK for
IMX7D_ENETx_IPG_ROOT_CLK instead of adding new clocks.
Based on Andy Duan's patch from the NXP kernel tree.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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i.MX6SX has lvds2 (analog clock2), an I/O clock like lvds1.
And this lvds2, along with lvds1, can be used to provide
external clock source to the internal pll, such as pll4_audio
and pll5_video.
This patch mainly adds the lvds2 to the clock tree and fix its
relationship with pll accordingly.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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and 'clk-qcom-mmagic' into clk-next
* clk-allwinner:
clk: sunxi-ng: r40: export a regmap to access the GMAC register
clk: sunxi-ng: r40: rewrite init code to a platform driver
clk: sunxi-ng: add support for H6 PRCM CCU
* clk-rockchip:
clk: rockchip: remove deprecated gate-clk code and dt-binding
clk: rockchip: use match_string() helper
* clk-tegra:
clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20
clk: tegra20: Correct parents of CDEV1/2 clocks
clk: tegra20: Add DEV1/DEV2 OSC dividers
* clk-berlin:
clk: berlin: switch to SPDX license identifier
* clk-qcom-mmagic:
clk: qcom: mmcc-msm8996: leave all mmagic gdscs and clocks always enabled
clk: qcom: Register the gdscs before the clocks
clk: qcom: gdsc: Add support for ALWAYS_ON gdscs
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The H6 has clock/reset controls in PRCM part, like old SoCs such as H3
and A64. However, the PRCM CCU is rearranged; the register arragement
is now similar to the main CCU of H6, and the PRCM now has two APB
buses to control -- one is clocked from AHB clock derivde from AR100
clock, the other is clocked from the same mux with AR100 clock.
Therefore a new driver is written for it.
As there's no official document about the PRCM in H6, all the information
are indirectly collected from BSP and parts of the document, and the
information source is noted as comments in the driver's source code. If
reliable information is provided furtherly, the driver needs to be
rechecked.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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