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* Merge tag 'clk-for-linus' of ↵Linus Torvalds2017-02-2525-364/+1527
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The usual collection of new drivers, non-critical fixes, and updates to existing clk drivers. The bulk of the work is on Allwinner and Rockchip SoCs, but there's also an Intel Atom driver in here too. New Drivers: - Tegra BPMP firmware - Hisilicon hi3660 SoCs - Rockchip rk3328 SoCs - Intel Atom PMC - STM32F746 - IDT VersaClock 5P49V5923 and 5P49V5933 - Marvell mv98dx3236 SoCs - Allwinner V3s SoCs Removed Drivers: - Samsung Exynos4415 SoCs Updates: - Migrate ABx500 to OF - Qualcomm IPQ4019 CPU clks and general PLL support - Qualcomm MSM8974 RPM - Rockchip non-critical fixes and clk id additions - Samsung Exynos4412 CPUs - Socionext UniPhier NAND and eMMC support - ZTE zx296718 i2s and other audio clks - Renesas CAN and MSIOF clks for R-Car M3-W - Renesas resets for R-Car Gen2 and Gen3 and RZ/G1 - TI CDCE913, CDCE937, and CDCE949 clk generators - Marvell Armada ap806 CPU frequencies - STM32F4* I2S/SAI support - Broadcom BCM2835 DSI support - Allwinner sun5i and A80 conversion to new style clk bindings" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (130 commits) clk: renesas: mstp: ensure register writes complete clk: qcom: Do not drop device node twice clk: mvebu: adjust clock handling for the CP110 system controller clk: mvebu: Expand mv98dx3236-core-clock support clk: zte: add i2s clocks for zx296718 clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR() clk: sunxi-ng: select SUNXI_CCU_MULT for sun5i clk: sunxi-ng: Check kzalloc() for errors and cleanup error path clk: tegra: Add BPMP clock driver clk: uniphier: add eMMC clock for LD11 and LD20 SoCs clk: uniphier: add NAND clock for all UniPhier SoCs ARM: dts: sun9i: Switch to new clock bindings clk: sunxi-ng: Add A80 Display Engine CCU clk: sunxi-ng: Add A80 USB CCU clk: sunxi-ng: Add A80 CCU clk: sunxi-ng: Support separately grouped PLL lock status register clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers clk: qcom: SDHCI enablement on Nexus 5X / 6P ...
| * Merge tag 'v4.11-rockchip-clk2' of ↵Stephen Boyd2017-02-031-0/+1
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull Rockchip clk updates from Heiko Stuebner: "Non-critical fix for the pclk_edp divider on rk3399, one new clock-id and making niu (interconnect) clocks critical on rk3288, as CLK_IGNORE_UNUSED is not enough to keep them running all the time when more users access particular clock subtrees." * tag 'v4.11-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: rk3288: make all niu clocks critical clk: rockchip: use rk3288 vip_out clock ids clk: rockchip: add rk3288 vip_out clock id clk: rockchip: fix the incorrect pclk_edp div width for RK3399
| | * clk: rockchip: add rk3288 vip_out clock idJacob Chen2017-01-221-0/+1
| | | | | | | | | | | | | | | | | | | | | Add clock-ids for the vip block of the rk3288 Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | Merge tag 'sunxi-clk-for-4.11' of ↵Stephen Boyd2017-02-0310-0/+837
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Pull Allwinner clock updates from Maxime Ripard: - Support for one new SoC, the V3s - Conversion of two old SoCs to the new framework, the old sun5i family and the A80 - A bunch of fixes * tag 'sunxi-clk-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (25 commits) ARM: dts: sun9i: Switch to new clock bindings clk: sunxi-ng: Add A80 Display Engine CCU clk: sunxi-ng: Add A80 USB CCU clk: sunxi-ng: Add A80 CCU clk: sunxi-ng: Support separately grouped PLL lock status register clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPU clk: sunxi-ng: Call divider_round_rate if we only have a single parent ARM: gr8: Convert to CCU ARM: sun5i: Convert to CCU clk: sunxi-ng: Add sun5i CCU driver clk: sunxi-ng: Implement global pre-divider clk: sunxi-ng: Implement multiplier maximum clk: sunxi-ng: mult: Fix minimum in round rate clk: sunxi-ng: Implement factors offsets clk: sunxi-ng: multiplier: Add fractional support clk: sunxi-ng: add support for V3s CCU dt-bindings: add device binding for the CCU of Allwinner V3s ...
| | * | clk: sunxi-ng: Add A80 Display Engine CCUChen-Yu Tsai2017-01-302-0/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the A80 SoC, Allwinner grouped and moved some subsystem specific clock controls to a separate address space, and possibly separate hardware block. One such subsystem is the display engine. The main clock control unit now only has 1 set of bus gate, dram gate, module clock, and reset control for the entire display subsystem. These feed into a secondary clock control unit, which has controls for each individual module of the display pipeline. This block is not documented in the user manual. Allwinner's kernel was used as the reference. Add support for the display engine clock controls found on the A80. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | clk: sunxi-ng: Add A80 USB CCUChen-Yu Tsai2017-01-302-0/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the USB clock controls found on the A80. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | clk: sunxi-ng: Add A80 CCUChen-Yu Tsai2017-01-302-0/+264
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the main clock unit found in the A80. Some clocks were not documented in the released user manual, but were found in the official kernel from Allwinner. These include controls for the I2S, SPDIF, SATA, and eDP blocks. Note that on the A80, some subsystems have separate clock controllers downstream of the main clock unit. These include the MMC, USB, and display engine subsystems. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | clk: sunxi-ng: Add sun5i CCU driverMaxime Ripard2017-01-232-0/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner A10s, A13, R8 and NextThing GR8 are all based on the same silicon, and all share the same clocks. However, they're not packaged in the same way, and therefore not all the controllers are actually available on all these SoCs. Introduce a clock controller driver for all these SoCs with different compatibles to take that into account. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | clk: sunxi-ng: add support for V3s CCUIcenowy Zheng2017-01-202-0/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | V3s has a similar but cut-down CCU to H3. Some muxes, especially clocks about CSI, are different, which makes it to need a new CCU driver. Add such a new driver for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | dt-bindings: qcom: clk: Add missing binding for SDCHI enablement on Nexus 5X/6PJeremy McNicoll2017-01-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AHB clock branch is needed in order to enable SDHCI on msm899(2/4). Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | Merge tag 'clk-v4.11-samsung-2' of git://linuxtv.org/snawrocki/samsung into ↵Stephen Boyd2017-01-271-1/+4
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-next Pull Samsung clk driver updates from Sylwester Nawrocki: - Exporting clock IDs for Exynos5433 SoC MIPI DSI DPHY - Exynos PLL code updates and overall minor clean-ups * tag 'clk-v4.11-samsung-2' of git://linuxtv.org/snawrocki/samsung: clk: samsung: mark s3c...._clk_sleep_init() as __init clk: samsung: Add enable/disable support for PLL35XX clocks clk: samsung: exynos5433: Correct typos in SoC name clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks
| | * | | clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocksMarek Szyprowski2017-01-271-1/+4
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed to setup initial clock configuration for display subsystem in device tree in order to avoid dependency on the configuration left by the bootloader. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * | | Merge branch 'clk-ux500' into clk-nextStephen Boyd2017-01-271-0/+11
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * clk-ux500: clk: ux500: Convert ABx500 clocks to use OF probing clk: ux500: Add device tree bindings for ABx500 clocks clk: ux500: move AB8500 sysclk over to PRCMU clk driver
| | * | | clk: ux500: Convert ABx500 clocks to use OF probingLinus Walleij2017-01-271-0/+11
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These clocks have been broken for a long time unfortunately, a hurdle of misc problems made them stop working at some point breaking USB and audio on Ux500. The platform as such and all "regular" clocks are migrated to OF/device tree, so let's migrate also this driver. With this patch and the corresponding DTS fixes, and a bunch of probe deferral fixes, audio starts working again on Ux500. Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | Merge branch 'clk-stm32f4' into clk-nextStephen Boyd2017-01-271-0/+20
| |\ \ \ | | | | | | | | | | | | | | | | | | | | * clk-stm32f4: clk: stm32f7: Add stm32f7 clock DT bindings for STM32F746 boards
| | * | | clk: stm32f7: Add stm32f7 clock DT bindings for STM32F746 boardsGabriel Fernandez2017-01-211-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces the stm32f7 clock DT bindings. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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| *-. \ \ \ Merge branch 'clk-imx7', 'clk-bcm2835' into clk-nextStephen Boyd2017-01-272-1/+4
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * clk-imx7: clk: imx7d: Add the OCOTP clock * clk-bcm2835: clk: bcm2835: Add leaf clock measurement support, disabled by default clk: bcm2835: Register the DSI0/DSI1 pixel clocks. clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL dividers.
| | | * | | | clk: bcm2835: Register the DSI0/DSI1 pixel clocks.Eric Anholt2017-01-211-0/+2
| | | | |/ / | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DSI pixel clocks are muxed from clocks generated in the analog phy by the DSI driver. In order to set them as parents, we need to do the same name lookup dance on them as we do for our root oscillator. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * / | | clk: imx7d: Add the OCOTP clockFabio Estevam2017-01-211-1/+2
| | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the OCOTP so that this hardware block can be used. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | | Merge tag 'v4.11-rockchip-clk1' of ↵Stephen Boyd2017-01-213-0/+403
| |\ \ \ \ | | | |_|/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull Rockchip clk updates from Heiko Stuebner: A new clock-type for the 1-2 muxes per soc that are for whatever reason controlled through the General Register Files, support for the rk3328 clock-controller (including a new pll-type) and the usual clock ids and some fixes. * tag 'v4.11-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: dt-bindings: clk: add rockchip,grf property for RK3399 clk: rockchip: use clock ids for memory controller parts on rk3066/rk3188 clk: rockchip: use rk3288 isp_in clock ids clk: rockchip: add clock ids for memory controller parts on rk3066/rk3188 clk: rockchip: add rk3288 isp_in clock ids clk: rockchip: Remove useless init of "grf" to -EPROBE_DEFER clk: rockchip: add clock controller for rk3328 dt-bindings: add bindings for rk3328 clock controller clk: rockchip: add dt-binding header for rk3328 clk: rockchip: add new pll-type for rk3328 clk: rockchip: describe aclk_vcodec using the new muxgrf type on rk3288 clk: rockchip: add a clock-type for muxes based in the grf
| | * | | clk: rockchip: add clock ids for memory controller parts on rk3066/rk3188Heiko Stuebner2017-01-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clock ids for the upctl and publ controllers used for ddr control. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * | | clk: rockchip: add rk3288 isp_in clock idsJacob Chen2017-01-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clock-ids for the isp block of the rk3288. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * | | clk: rockchip: add dt-binding header for rk3328Elaine Zhang2017-01-051-0/+400
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the dt-bindings header for the rk3328, that gets shared between the clock controller and the clock references in the dts. Add softreset ID for rk3328. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | | Merge tag 'clk-v4.11-samsung' of git://linuxtv.org/snawrocki/samsung into ↵Stephen Boyd2017-01-211-360/+0Star
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-next Pull Samsung clk updates from Sylwester Nawrocki: - addition of the CPU clock configuration data for Exynos4412 Prime SoC variant, - removal of driver for deprecated Exynos4415 SoC, - switching from the syscore to regular system sleep PM ops in the audio subsystem clocks controller driver, - updates of the definitions of some "Network On Chip" related clocks. * tag 'clk-v4.11-samsung' of git://linuxtv.org/snawrocki/samsung: clk: samsung: Remove Exynos4415 driver (SoC not supported anymore) clk: samsung: exynos-audss: Replace syscore PM with platform device PM clk: samsung: exynos5433: Set NoC (Network On Chip) clocks as critical clk: samsung: Add CPU clk configuration data for Exynos4412 Prime
| | * | | clk: samsung: Remove Exynos4415 driver (SoC not supported anymore)Krzysztof Kozlowski2017-01-161-360/+0Star
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support for Exynos4415 is going away because there are no internal nor external users. Since commit 46dcf0ff0de3 ("ARM: dts: exynos: Remove exynos4415.dtsi"), the platform cannot be instantiated so remove also the drivers. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Kukjin Kim <kgene@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * | | clk: mdm9615: Add EBI2 clockZoran Markovic2017-01-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add definition of EBI2 clock used by MDM9615 NAND controller. Cc: Andy Gross <andy.gross@linaro.org> Cc: David Brown <david.brown@linaro.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-msm@vger.kernel.org Cc: linux-soc@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Zoran Markovic <zmarkovic@sierrawireless.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> [sboyd@codeaurora.org: ebi2_clk halt bit is 24 not 23] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | Merge branch 'clk-hi3660' into clk-nextStephen Boyd2017-01-101-0/+194
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | * clk-hi3660: clk: hisilicon: Add clock driver for hi3660 SoC dt-bindings: Document the hi3660 clock bindings
| | * | | clk: hisilicon: Add clock driver for hi3660 SoCZhangfei Gao2017-01-101-0/+194
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clock drivers for hi3660 SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> [sboyd@codeaurora.org: Simplify probe with function pointer] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: qcom: Add GCC_MSS_RESET supportAvaneesh Kumar Dwivedi2017-01-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to use reset control framework for resetting MSS with hexagon v56 1.5.0. Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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| *-----. \ \ Merge branches 'clk-qcom-rpm8974', 'clk-stm32f4', 'clk-ipq4019' and ↵Stephen Boyd2017-01-103-2/+88
| |\ \ \ \ \ \ | | |_|_|_|/ / | |/| | | | / | | | | |_|/ | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-fixes' into clk-next * clk-qcom-rpm8974: clk: qcom: smd-rpmcc: Add msm8974 clocks * clk-stm32f4: clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board clk: stm32f4: Add SAI clocks clk: stm32f4: Add I2S clock clk: stm32f4: Add lcd-tft clock clk: stm32f4: Add post divisor for I2S & SAI PLLs clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards clk: stm32f4: Update DT bindings documentation * clk-ipq4019: clk: qcom: ipq4019: Add the cpu clock frequency change notifier clk: qcom: ipq4019: Add all the frequencies for apss cpu clk: qcom: ipq4019: correct sdcc frequency and parent name clk: qcom: ipq4019: Add the nodes for pcnoc clk: qcom: ipq4019: Add the apss cpu pll divider clock node clk: qcom: ipq4019: remove fixed clocks and add pll clocks * clk-fixes: clk: stm32f4: Use CLK_OF_DECLARE_DRIVER initialization method clk: renesas: mstp: Support 8-bit registers for r7s72100
| | | | * | clk: qcom: ipq4019: Add the nodes for pcnocAbhishek Sahu2016-12-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current ipq4019 clock driver does not have the node for PCNOC so this patch adds and registers the PCNOC clock nodes. This PCNOC clock is critical and should not be turned off so setting CRITICAL flag also. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | | | * | clk: qcom: ipq4019: Add the apss cpu pll divider clock nodeAbhishek Sahu2016-12-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current ipq4019 clock driver does not have support for all the frequency supported by APSS CPU. APSS CPU frequency is provided with APSS CPU PLL divider which divides down the VCO frequency. This divider is nonlinear and specific to IPQ4019 so the standard divider code cannot be used for this. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | | | * | clk: qcom: ipq4019: remove fixed clocks and add pll clocksAbhishek Sahu2016-12-221-0/+9
| | | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current ipq4019 clock driver registered the PLL clocks and dividers as fixed clock. These fixed clock needs to be removed from driver probe function and same need to be registered with clock framework. These PLL clocks should be programmed only once and the same are being programmed already by the boot loader so the set rate operation is not required for these clocks. Only the rate can be calculated by clock operations in clock driver file so this patch adds the same. The PLL takes the reference clock from XO and generates the intermediate VCO frequency. This VCO frequency will be divided down by different PLL internal dividers. Some of the PLL internal dividers are fixed while other are programmable. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * | / clk: qcom: smd-rpmcc: Add msm8974 clocksBjorn Andersson2016-12-221-2/+38
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds all RPM based clocks for msm8974, except cxo and gfx3d_clk_src. Tested-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | | | Merge tag 'armsoc-drivers' of ↵Linus Torvalds2017-02-242-0/+42
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Arnd Bergmann: "Driver updates for ARM SoCs. A handful of driver changes this time around. The larger changes are: - Reset drivers for hi3660 and zx2967 - AHCI driver for Davinci, acked by Tejun and brought in here due to platform dependencies - Cleanups of atmel-ebi (External Bus Interface) - Tweaks for Rockchip GRF (General Register File) usage (kitchensink misc register range on the SoCs) - PM domains changes for support of two new ZTE SoCs (zx296718 and zx2967)" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (53 commits) soc: samsung: pmu: Add register defines for pad retention control reset: make zx2967 explicitly non-modular reset: core: fix reset_control_put soc: samsung: pm_domains: Read domain name from the new label property soc: samsung: pm_domains: Remove message about failed memory allocation soc: samsung: pm_domains: Remove unused name field soc: samsung: pm_domains: Use full names in subdomains registration log sata: ahci-da850: un-hardcode the MPY bits sata: ahci-da850: add a workaround for controller instability sata: ahci: export ahci_do_hardreset() locally sata: ahci-da850: implement a workaround for the softreset quirk sata: ahci-da850: add device tree match table sata: ahci-da850: get the sata clock using a connection id soc: samsung: pmu: Remove duplicated define for ARM_L2_OPTION register memory: atmel-ebi: Enable the SMC clock if specified soc: samsung: pmu: Remove unused and duplicated defines memory: atmel-ebi: Properly handle multiple reference to the same CS memory: atmel-ebi: Fix the test to enable generic SMC logic soc: samsung: pm_domains: Add new Exynos5433 compatible soc: samsung: pmu: Add dummy support for Exynos5433 SoC ...
| * \ \ \ Merge tag 'zte-pd-4.11' of ↵Olof Johansson2017-01-301-0/+24
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/drivers ZTE PM domain driver support for 4.11: - It includes a series which adds DT bindings and PM domain driver for PCU (Power Control Unit) block found on ZTE ZX2967 family SoC. * tag 'zte-pd-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: soc: zte: pm_domains: Add support for zx296718 soc: zte: pm_domains: Prepare for supporting ARMv8 zx2967 family soc: zte: Add header for PM domains specifiers MAINTAINERS: add zx2967 SoC drivers to ARM ZTE architecture dt-bindings: zte: add bindings document for zx2967 power domain controller Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | soc: zte: Add header for PM domains specifiersBaoyou Xie2017-01-111-0/+24
| | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds header with values used for ZTE 2967 SoC's power domain driver. Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * | | | Merge tag 'v4.11-armsoc-drivers1' of ↵Olof Johansson2017-01-291-0/+18
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/drivers Some extensions to the power-domain driver to support domains in hiword registers (write-mask in upper 16bit) and domain-definitions for the rk3328 soc. Secondly a "driver" that attaches to the already existing grf nodes and is able to set static defaults for settings that cannot really be attached to any specific subsystem. Most GRF settings can already be set from drivers using them, but there are some behavioural settings like the mmc/jtag switch that cannot. As the commit message states this is really meant as a last line of defence for things that neither belong to a subsystem nor to the Having this here allows arm64 socs to have this as well and also moves another bit of code out of the arm32 mach-rockchip. * tag 'v4.11-armsoc-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: rockchip: drop rk3288 jtag/mmc switch handling soc: rockchip: add driver handling grf setup dt-bindings: add used but undocumented rockchip grf compatible values soc: rockchip: power-domain: add power domain support for rk3328 dt-bindings: add binding for rk3328 power domains dt-bindings: power: add RK3328 SoCs header for idle-request soc: rockchip: power-domain: Support domain control in hiword-registers Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | dt-bindings: power: add RK3328 SoCs header for idle-requestElaine Zhang2017-01-051-0/+18
| | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to a description from TRM, add all the idle request. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | | | | Merge tag 'armsoc-dt64' of ↵Linus Torvalds2017-02-241-0/+14
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM 64-bit DT updates from Arnd Bergmann: "ARM64 DT updates are fairly small this time, only two new SoCs and a handful of new machines get added, all of them similar to other hardware we already support. New SoC: - HiSilicon Kirin960/Hi3660 and HiKey960 development board - NXP LS1012a with three reference boards: http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/qoriq-layerscape-arm-processors/qoriq-layerscape-1012a-low-power-communication-processor:LS1012A New development board: - Banana Pi M64, based on Allwinner A64: http://www.banana-pi.org/m64.html - SolidRun MACCHIATOBin based on Marvell Armada 8K: https://www.solid-run.com/marvell-armada-family/armada-8040-community-board/ - Broadcom BCM958712DxXMC NorthStar2 reference board (another one) A lot of platforms improve support for existing machines by adding extra devices for which a binding and driver is availabe: Allwinner: - MMC, USB ARM Juno: - Coresight, STM Broadcom: - NS2 GICv2m irqchip and PCIe Marvell: - Armada 3700 SPI, I2C, ethernet switch Mediatek: - MT8173 thermal NXP i.MX: - LS1046A thermal Qualcomm: - coresight on MSM8916, HDMI, WCNSS, SCM Renesas: - r8a779[56] thermal, powerdomain, ethernet, sound, pwm, can, can fd Rockchip: - thermal, eDP, pinctrl enhancements Samsung: - TM2 touchkey, Exynos5433 HDMI and power management improvements UniPhier: - SD reset, eMMC controller ZTE: - oppv2 cpufreq" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (110 commits) arm64: dts: qcom: Add msm8916 CoreSight components arm64: dts: marvell: adjust name of sd-mmc-gop clock in syscon arm64: allwinner: add BananaPi-M64 support arm64: allwinner: a64: add UART1 pin nodes arm64: allwinner: pine64: add MMC support arm64: allwinner: a64: Increase the MMC max frequency arm64: allwinner: a64: Add MMC pinctrl nodes arm64: allwinner: a64: Add MMC nodes dt-bindings: clockgen: Add compatible string for LS1012A Documentation: DT: add LS1012A compatible for SCFG and DCFG Documentation: DT: Add entry for FSL LS1012A RDB, FRDM, QDS boards arm64: dts: marvell: add generic-ahci compatibles for CP110 ahci arm64: tegra: Use symbolic reset identifiers arm64: dts: r8a7796: Mark EthernetAVB device node disabled arm64: dts: r8a7795: Mark EthernetAVB device node disabled arm64: dts: r8a7795: tidyup audma definition order arm64: dts: r8a7796: Link ARM GIC to clock and clock domain arm64: dts: r8a7795: Link ARM GIC to clock and clock domain arm64: dts: r8a7796: Add R-Car Gen3 thermal support arm64: dts: r8a7795: Add R-Car Gen3 thermal support ...
| * \ \ \ \ Merge tag 'samsung-dt64-4.11' of ↵Olof Johansson2017-01-171-0/+14
| |\ \ \ \ \ | | |/ / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64 Samsung DeviceTree ARM64 update for v4.11: 1. Add bus frequency and voltage scalling on Exynos5433 TM2 device (along with necessary bus nodes and Platform Performance Monitoring Unit on Exynos5433). 2. Use macros for pinctrl settings on Exynos5433. This contains necessary header with bindings. 3. Minor cleanups in Exynos5433 DTSI and boards using it. 4. Create common DTSI betweem Exynos5433 TM2E and TM2E. 5. Add HDMI/TV to Exynos5433 TM2. * tag 'samsung-dt64-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: exynos: Enable HDMI/TV path on Exynos5433-TM2 arm64: dts: exynos: Add HDMI node to Exynos5433 arm64: dts: exynos: Add DECON_TV node to Exynos5433 arm64: dts: exynos: Fix addresses in node names on Exynos5433 arm64: dts: exynos: Make TM2 and TM2E independent from each other arm64: dts: exynos: Fix wrong values for ldo23 and ldo25 on TM2/TM2E arm64: dts: exynos: Remove unsupported regulator-always-off property from TM2E arm64: dts: exynos: Comply to the samsung pinctrl naming convention in TM2 arm64: dts: exynos: Use macros for pinctrl configuration on Exynos5433 pinctrl: dt-bindings: samsung: add drive strength macros for Exynos5433 arm64: dts: exynos: Add support of bus frequency using VDD_INT on Exynos5433 TM2 arm64: dts: exynos: Add bus nodes using VDD_INT for Exynos5433 arm64: dts: exynos: Add PPMU node to Exynos5433 Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | pinctrl: dt-bindings: samsung: add drive strength macros for Exynos5433Andi Shyti2017-01-061-0/+14
| | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 5db7e3bb87df ("pinctrl: dt-bindings: samsung: Add header with values used for configuration") has added a header file for defining the pinctrl values in order to avoid hardcoded settings in the Exynos DTS related files. Extend samsung.h to the Exynos5433 for drive strength values which are strictly related to the particular SoC and may defer from others. Signed-off-by: Andi Shyti <andi.shyti@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
* | | | | Merge tag 'armsoc-dt' of ↵Linus Torvalds2017-02-243-7/+60
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Arnd Bergmann: "A total of 380 patches this time, mostly adding support for more hardware in the device tree descriptions. There is not much exciting here for 4.11, but I've tried my best to condense the information from the pull requests I got into a readable summary. Noteworthy changes to existing platforms include: - The GIC memory map was a bit wrong almost everywhere and now gets fixed up - The Allwinner platforms convert to the generic pinmux properties - The Marvell EBU platforms now use the new DSA binding - Samsung Exynos4212 was unused and gets removed - The Renesas power management got improved New production machines: - Lego Mindstorms EV3: https://www.lego.com/en-us/mindstorms/about-ev3 - Beelink X2 Android media box: http://linux-sunxi.org/Beelink_X2 - "Romulus" baseboard management controller for OpenPower - Axentia TSE-850 Data Radio Channel (DARC) encoder: http://www.axentia.se/db/equipment.html - Luxul XAP-1410 and XWR-1200 wireless access points: https://luxul.com/xap-1410 New SoCs: - Allwinner H2+ and V3s, both minor variations of already supported chips: http://www.allwinnertech.com/index.php?c=product&a=index&id=38 - Marvell Prestera DX packet processors based on Armada XP architecture: http://www.marvell.com/switching/prestera-dx/ - Samsung Exynos4412 Prime gets added, a minor variation of Exynos4412 New developer and reference boards: - Lichee Pi One, Lichee Pi Zero and Orange Pi Zero, all based on Allwinner SoCs: http://linux-sunxi.org/LicheePi_One http://www.orangepi.org/orangepizero/ - SAMA5d36ek Reference platform: http://www.atmel.com/tools/sama5d36-ek.aspx - Beaglebone Green Wireless and Black Wireless: https://beagleboard.org/black-wireless https://beagleboard.org/green-wireless - phyCORE-AM335x System on Module: http://phytec.com/products/system-on-modules/phycore/am335x/ - New revision of "vf610-zii" Zodiac Inflight Innovations board - Various i.MX System-on-Module: Is.IoT MX6UL, SavageBoard, Engicam i.Core: http://www.opossom.com/english/index.html http://www.savageboard.org/ http://www.engicam.com/en/products/embedded/som/sodimm/is-iot-mx6ul http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q - Liebherr (LWN) monitor 6 based on i.MX6 Quad, no idea what this is - Cleanups and bugfixes on at91, bcm53xx, i.MX, mvebu, omap, oxnas, qcom, rockchip, sti, stm32 and tegra New device supports added to some boards and SoCs, briefly by platform: - Allwinner: SPDIF, A33 cpufreq, A33 Mali GPU - Aspeed: network, ipmi bt, gpio, pinmux - Broadcom: video encoder for raspberry pi, qspi, ethernet, sd/mmc - TI DaVinci: gpio, lcdc, usb, video-in, uart - TI Keystone 2: MSM RAM, power/reset, uart - Mediatek MT2701: clocks, iommu, spi, nand, adc, thermal - Marvell EBU: ethernet switch on Turris Omnia - NXP i.MX: otp ram, USB, wifi, bluetooth, spdif, spi, pmic, eeprom, mmc, nand - TI OMAP: - Qualcomm: coresight, gyro/accelerometer, hdmi - Renesas: pmic, soc-id - Rockchip: qos - Samsung: audio on Odroid-X - Socfpga: FPGA manager, i2c, led, can, watchdog, nand, power monitor - STi: video in/out - STM32: timer, pwm, i2c, rtc, add, i2s - NVIDIA Tegra: tpm - Uniphier: mmc/sd pinmux" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (380 commits) ARM: dts: armada-385-linksys: fix DSA compatible property ARM: dts: Fix typo in armada-xp-98dx4251 ARM: DTS: Fix register map for virt-capable GIC dt-bindings: arm,gic: Fix binding example for a virt-capable GIC ARM: dts: sun8i: sinlinx: Enable audio nodes ARM: dts: sun8i: parrot: Enable audio nodes ARM: dts: sun8i: Add audio codec, dai and card for A33 ARM: dts: Add EMAC AXI settings for Arria10 ARM: dts: am335x-chiliboard: Support charger ARM: dts: am335x-chiliboard: Support power button ARM: sun8i: dt: Add mali node dt-bindings: gpu: Add Mali Utgard bindings ARM: dts: stm32: Add I2C1 support for STM32429 eval board ARM: dts: stm32: Add I2C1 support for STM32F429 SoC ARM: dts: stm32: Use clock DT binding definition on stm32f429 family dt-bindings: mfd: stm32f4: Add missing binding definition dt-bindings: mfd: stm32f4: Fix STM32F4_X_CLOCK() macro ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco ARM: dts: stm32: add Timers driver for stm32f429 MCU ARM: dts: add the AB8500 sysclk to the device trees ...
| * \ \ \ \ Merge tag 'stm32-dt-for-v4.11-2' of ↵Arnd Bergmann2017-02-071-7/+17
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into next/dt Pull "STM32 DT updates for v4.11, round 2" from Alexandre Torgue: Highlights: ---------- - ADD Timers support on STM32F429 MCU - Enable PWM1 & PWM3 on STM32F469 Disco board - Fix STM32F4_X_CLOCK macro - Use STM32F4_X_CLOCK macro in STM32 device tree - Add I2C1 support for STM32F429 MCU - Enable I2C1 on STM32F429 eval board * tag 'stm32-dt-for-v4.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: ARM: dts: stm32: Add I2C1 support for STM32429 eval board ARM: dts: stm32: Add I2C1 support for STM32F429 SoC ARM: dts: stm32: Use clock DT binding definition on stm32f429 family dt-bindings: mfd: stm32f4: Add missing binding definition dt-bindings: mfd: stm32f4: Fix STM32F4_X_CLOCK() macro ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco ARM: dts: stm32: add Timers driver for stm32f429 MCU
| | * | | | | dt-bindings: mfd: stm32f4: Add missing binding definitionGabriel Fernandez2017-02-011-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds missing binding definition (backupram, ethernet, otg, qspi, adc & dsi) Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
| | * | | | | dt-bindings: mfd: stm32f4: Fix STM32F4_X_CLOCK() macroGabriel Fernandez2017-02-011-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Macro to select a clock was not correct. Offset of enable register starts at 0x30, then calculation to select a bit is: (@enable_reg - 0x30) / 4 * 32 + bit_to_select Tested-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
| | * | | | | Merge commit 'f8b5036361412a27c07a4ac9c3a4b80678cbd1e1' into stm32-dt-for-v4.11Alexandre TORGUE2017-01-201-0/+39
| | |\ \ \ \ \ | | | |_|/ / / | | |/| | | / | | | | |_|/ | | | |/| |
| | | * | | clk: stm32f4: Update DT bindings documentationGabriel Fernandez2016-12-221-0/+39
| | | | |/ | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Creation of dt include file for specific stm32f4 clocks. These specific clocks are not derived from system clock (SYSCLOCK) We should use index 1 to use these clocks in DT. e.g. <&rcc 1 CLK_LSI> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | | Merge tag 'renesas-dt2-for-v4.11' of ↵Olof Johansson2017-01-301-0/+4
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Second Round of Renesas ARM Based SoC DT Updates for v4.11 Enhancements: - Add power-domains to mmcif on r7s72100 SoC - Add OSTM to rskrza1/r7s72100 - Link ARM GIC to clock and clock domain on r8a774[35] SoCs Clean-up: - Correct SATA device status on r8a7779/marzen * tag 'renesas-dt2-for-v4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: dts: r7s72100: add power-domains to mmcif ARM: dts: rskrza1: add ostm DT support ARM: dts: r7s72100: add ostm to device tree ARM: dts: r7s72100: add ostm clock to device tree ARM: dts: r8a7745: Link ARM GIC to clock and clock domain ARM: dts: r8a7743: Link ARM GIC to clock and clock domain ARM: dts: r8a7779, marzen: Fix sata device status Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | ARM: dts: r7s72100: add ostm clock to device treeChris Brandt2017-01-241-0/+4
| | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-23 13:14:57 +0200