summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/highbank.dts
blob: 6aad34ad9517f37424071dcac4859c400a93d1f5 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
/*
 * Copyright 2011-2012 Calxeda, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

/dts-v1/;

/* First 4KB has pen for secondary cores. */
/memreserve/ 0x00000000 0x0001000;

/ {
	model = "Calxeda Highbank";
	compatible = "calxeda,highbank";
	#address-cells = <1>;
	#size-cells = <1>;
	clock-ranges;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@900 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0x900>;
			next-level-cache = <&L2>;
			clocks = <&a9pll>;
			clock-names = "cpu";
			operating-points = <
				/* kHz    ignored */
				 1300000  1000000
				 1200000  1000000
				 1100000  1000000
				  800000  1000000
				  400000  1000000
				  200000  1000000
			>;
			clock-latency = <100000>;
		};

		cpu@901 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0x901>;
			next-level-cache = <&L2>;
			clocks = <&a9pll>;
			clock-names = "cpu";
		};

		cpu@902 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0x902>;
			next-level-cache = <&L2>;
			clocks = <&a9pll>;
			clock-names = "cpu";
		};

		cpu@903 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0x903>;
			next-level-cache = <&L2>;
			clocks = <&a9pll>;
			clock-names = "cpu";
		};
	};

	memory {
		name = "memory";
		device_type = "memory";
		reg = <0x00000000 0xff900000>;
	};

	soc {
		ranges = <0x00000000 0x00000000 0xffffffff>;

		timer@fff10600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xfff10600 0x20>;
			interrupts = <1 13 0xf01>;
			clocks = <&a9periphclk>;
		};

		watchdog@fff10620 {
			compatible = "arm,cortex-a9-twd-wdt";
			reg = <0xfff10620 0x20>;
			interrupts = <1 14 0xf01>;
			clocks = <&a9periphclk>;
		};

		intc: interrupt-controller@fff11000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			#size-cells = <0>;
			#address-cells = <1>;
			interrupt-controller;
			reg = <0xfff11000 0x1000>,
			      <0xfff10100 0x100>;
		};

		L2: l2-cache {
			compatible = "arm,pl310-cache";
			reg = <0xfff12000 0x1000>;
			interrupts = <0 70 4>;
			cache-unified;
			cache-level = <2>;
		};

		pmu {
			compatible = "arm,cortex-a9-pmu";
			interrupts = <0 76 4  0 75 4  0 74 4  0 73 4>;
		};


		sregs@fff3c200 {
			compatible = "calxeda,hb-sregs-l2-ecc";
			reg = <0xfff3c200 0x100>;
			interrupts = <0 71 4  0 72 4>;
		};

	};
};

/include/ "ecx-common.dtsi"