include/asm-powerpc/elf.h


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#ifndef _ASM_POWERPC_ELF_H
#define _ASM_POWERPC_ELF_H

#include <linux/sched.h>	/* for task_struct */
#include <asm/types.h>
#include <asm/ptrace.h>
#include <asm/cputable.h>
#include <asm/auxvec.h>
#include <asm/page.h>
#include <asm/string.h>

/* PowerPC relocations defined by the ABIs */
#define R_PPC_NONE		0
#define R_PPC_ADDR32		1	/* 32bit absolute address */
#define R_PPC_ADDR24		2	/* 26bit address, 2 bits ignored.  */
#define R_PPC_ADDR16		3	/* 16bit absolute address */
#define R_PPC_ADDR16_LO		4	/* lower 16bit of absolute address */
#define R_PPC_ADDR16_HI		5	/* high 16bit of absolute address */
#define R_PPC_ADDR16_HA		6	/* adjusted high 16bit */
#define R_PPC_ADDR14		7	/* 16bit address, 2 bits ignored */
#define R_PPC_ADDR14_BRTAKEN	8
#define R_PPC_ADDR14_BRNTAKEN	9
#define R_PPC_REL24		10	/* PC relative 26 bit */
#define R_PPC_REL14		11	/* PC relative 16 bit */
#define R_PPC_REL14_BRTAKEN	12
#define R_PPC_REL14_BRNTAKEN	13
#define R_PPC_GOT16		14
#define R_PPC_GOT16_LO		15
#define R_PPC_GOT16_HI		16
#define R_PPC_GOT16_HA		17
#define R_PPC_PLTREL24		18
#define R_PPC_COPY		19
#define R_PPC_GLOB_DAT		20
#define R_PPC_JMP_SLOT		21
#define R_PPC_RELATIVE		22
#define R_PPC_LOCAL24PC		23
#define R_PPC_UADDR32		24
#define R_PPC_UADDR16		25
#define R_PPC_REL32		26
#define R_PPC_PLT32		27
#define R_PPC_PLTREL32		28
#define R_PPC_PLT16_LO		29
#define R_PPC_PLT16_HI		30
#define R_PPC_PLT16_HA		31
#define R_PPC_SDAREL16		32
#define R_PPC_SECTOFF		33
#define R_PPC_SECTOFF_LO	34
#define R_PPC_SECTOFF_HI	35
#define R_PPC_SECTOFF_HA	36

/* PowerPC relocations defined for the TLS access ABI.  */
#define R_PPC_TLS		67 /* none	(sym+add)@tls */
#define R_PPC_DTPMOD32		68 /* word32	(sym+add)@dtpmod */
#define R_PPC_TPREL16		69 /* half16*	(sym+add)@tprel */
#define R_PPC_TPREL16_LO	70 /* half16	(sym+add)@tprel@l */
#define R_PPC_TPREL16_HI	71 /* half16	(sym+add)@tprel@h */
#define R_PPC_TPREL16_HA	72 /* half16	(sym+add)@tprel@ha */
#define R_PPC_TPREL32		73 /* word32	(sym+add)@tprel */
#define R_PPC_DTPREL16		74 /* half16*	(sym+add)@dtprel */
#define R_PPC_DTPREL16_LO	75 /* half16	(sym+add)@dtprel@l */
#define R_PPC_DTPREL16_HI	76 /* half16	(sym+add)@dtprel@h */
#define R_PPC_DTPREL16_HA	77 /* half16	(sym+add)@dtprel@ha */
#define R_PPC_DTPREL32		78 /* word32	(sym+add)@dtprel */
#define R_PPC_GOT_TLSGD16	79 /* half16*	(sym+add)@got@tlsgd */
#define R_PPC_GOT_TLSGD16_LO	80 /* half16	(sym+add)@got@tlsgd@l */
#define R_PPC_GOT_TLSGD16_HI	81 /* half16	(sym+add)@got@tlsgd@h */
#define R_PPC_GOT_TLSGD16_HA	82 /* half16	(sym+add)@got@tlsgd@ha */
#define R_PPC_GOT_TLSLD16	83 /* half16*	(sym+add)@got@tlsld */
#define R_PPC_GOT_TLSLD16_LO	84 /* half16	(sym+add)@got@tlsld@l */
#define R_PPC_GOT_TLSLD16_HI	85 /* half16	(sym+add)@got@tlsld@h */
#define R_PPC_GOT_TLSLD16_HA	86 /* half16	(sym+add)@got@tlsld@ha */
#define R_PPC_GOT_TPREL16	87 /* half16*	(sym+add)@got@tprel */
#define R_PPC_GOT_TPREL16_LO	88 /* half16	(sym+add)@got@tprel@l */
#define R_PPC_GOT_TPREL16_HI	89 /* half16	(sym+add)@got@tprel@h */
#define R_PPC_GOT_TPREL16_HA	90 /* half16	(sym+add)@got@tprel@ha */
#define R_PPC_GOT_DTPREL16	91 /* half16*	(sym+add)@got@dtprel */
#define R_PPC_GOT_DTPREL16_LO	92 /* half16*	(sym+add)@got@dtprel@l */
#define R_PPC_GOT_DTPREL16_HI	93 /* half16*	(sym+add)@got@dtprel@h */
#define R_PPC_GOT_DTPREL16_HA	94 /* half16*	(sym+add)@got@dtprel@ha */

/* keep this the last entry. */
#define R_PPC_NUM		95

/*
 * ELF register definitions..
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
#include <asm/ptrace.h>

#define ELF_NGREG	48	/* includes nip, msr, lr, etc. */
#define ELF_NFPREG	33	/* includes fpscr */

typedef unsigned long elf_greg_t64;
typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];

typedef unsigned int elf_greg_t32;
typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];

/*
 * ELF_ARCH, CLASS, and DATA are used to set parameters in the core dumps.
 */
#ifdef __powerpc64__
# define ELF_NVRREG32	33	/* includes vscr & vrsave stuffed together */
# define ELF_NVRREG	34	/* includes vscr & vrsave in split vectors */
# define ELF_GREG_TYPE	elf_greg_t64
#else
# define ELF_NEVRREG	34	/* includes acc (as 2) */
# define ELF_NVRREG	33	/* includes vscr */
# define ELF_GREG_TYPE	elf_greg_t32
# define ELF_ARCH	EM_PPC
# define ELF_CLASS	ELFCLASS32
# define ELF_DATA	ELFDATA2MSB
#endif /* __powerpc64__ */

#ifndef ELF_ARCH
# define ELF_ARCH	EM_PPC64
# define ELF_CLASS	ELFCLASS64
# define ELF_DATA	ELFDATA2MSB
  typedef elf_greg_t64 elf_greg_t;
  typedef elf_gregset_t64 elf_gregset_t;
# define elf_addr_t unsigned long
#else
  /* Assumption: ELF_ARCH == EM_PPC and ELF_CLASS == ELFCLASS32 */
  typedef elf_greg_t32 elf_greg_t;
  typedef elf_gregset_t32 elf_gregset_t;
# define elf_addr_t u32
#endif /* ELF_ARCH */

/* Floating point registers */
typedef double elf_fpreg_t;
typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];

/* Altivec registers */
/*
 * The entries with indexes 0-31 contain the corresponding vector registers. 
 * The entry with index 32 contains the vscr as the last word (offset 12) 
 * within the quadword.  This allows the vscr to be stored as either a 
 * quadword (since it must be copied via a vector register to/from storage) 
 * or as a word.  
 *
 * 64-bit kernel notes: The entry at index 33 contains the vrsave as the first  
 * word (offset 0) within the quadword.
 *
 * This definition of the VMX state is compatible with the current PPC32 
 * ptrace interface.  This allows signal handling and ptrace to use the same 
 * structures.  This also simplifies the implementation of a bi-arch 
 * (combined (32- and 64-bit) gdb.
 *
 * Note that it's _not_ compatible with 32 bits ucontext which stuffs the
 * vrsave along with vscr and so only uses 33 vectors for the register set
 */
typedef __vector128 elf_vrreg_t;
typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
#ifdef __powerpc64__
typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
#endif

/*
 * This is used to ensure we don't load something for the wrong architecture.
 */
#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH)

#define USE_ELF_CORE_DUMP
#define ELF_EXEC_PAGESIZE	PAGE_SIZE

/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
   use of this is to invoke "./ld.so someprog" to test out a new version of
   the loader.  We need to make sure that it is out of the way of the program
   that it will "exec", and that there is sufficient room for the brk.  */

#define ELF_ET_DYN_BASE         (0x08000000)

#ifdef __KERNEL__

/* Common routine for both 32-bit and 64-bit processes */
static inline void ppc_elf_core_copy_regs(elf_gregset_t elf_regs,
					    struct pt_regs *regs)
{
	int i, nregs;

	memset((void *)elf_regs, 0, sizeof(elf_gregset_t));

	/* Our registers are always unsigned longs, whether we're a 32 bit
	 * process or 64 bit, on either a 64 bit or 32 bit kernel.
	 * Don't use ELF_GREG_TYPE here. */
	nregs = sizeof(struct pt_regs) / sizeof(unsigned long);
	if (nregs > ELF_NGREG)
		nregs = ELF_NGREG;

	for (i = 0; i < nregs; i++) {
		/* This will correctly truncate 64 bit registers to 32 bits
		 * for a 32 bit process on a 64 bit kernel. */
		elf_regs[i] = (elf_greg_t)((ELF_GREG_TYPE *)regs)[i];
	}
}
#define ELF_CORE_COPY_REGS(gregs, regs) ppc_elf_core_copy_regs(gregs, regs);

static inline int dump_task_regs(struct task_struct *tsk,
				 elf_gregset_t *elf_regs)
{
	struct pt_regs *regs = tsk->thread.regs;
	if (regs)
		ppc_elf_core_copy_regs(*elf_regs, regs);

	return 1;
}
#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)

extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); 
#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs)

#endif /* __KERNEL__ */

/* ELF_HWCAP yields a mask that user programs can use to figure out what
   instruction set this cpu supports.  This could be done in userspace,
   but it's not easy, and we've already done it here.  */
# define ELF_HWCAP	(cur_cpu_spec->cpu_user_features)
#ifdef __powerpc64__
# define ELF_PLAT_INIT(_r, load_addr)	do {	\
	_r->gpr[2] = load_addr; 		\
} while (0)
#endif /* __powerpc64__ */

/* This yields a string that ld.so will use to load implementation
   specific libraries for optimization.  This is more specific in
   intent than poking at uname or /proc/cpuinfo.

   For the moment, we have only optimizations for the Intel generations,
   but that could change... */

#define ELF_PLATFORM	(NULL)

#ifdef __KERNEL__

#ifdef __powerpc64__
# define SET_PERSONALITY(ex, ibcs2)				\
do {								\
	unsigned long new_flags = 0;				\
	if ((ex).e_ident[EI_CLASS] == ELFCLASS32)		\
		new_flags = _TIF_32BIT;				\
	if ((current_thread_info()->flags & _TIF_32BIT)		\
	    != new_flags)					\
		set_thread_flag(TIF_ABI_PENDING);		\
	else							\
		clear_thread_flag(TIF_ABI_PENDING);		\
	if (personality(current->personality) != PER_LINUX32)	\
		set_personality(PER_LINUX);			\
} while (0)
/*
 * An executable for which elf_read_implies_exec() returns TRUE will
 * have the READ_IMPLIES_EXEC personality flag set automatically. This
 * is only required to work around bugs in old 32bit toolchains. Since
 * the 64bit ABI has never had these issues dont enable the workaround
 * even if we have an executable stack.
 */
# define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \
		(exec_stk != EXSTACK_DISABLE_X) : 0)
#else 
# define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
#endif /* __powerpc64__ */

#endif /* __KERNEL__ */

extern int dcache_bsize;
extern int icache_bsize;
extern int ucache_bsize;

#ifdef __powerpc64__
struct linux_binprm;
#define ARCH_HAS_SETUP_ADDITIONAL_PAGES	/* vDSO has arch_setup_additional_pages */
extern int arch_setup_additional_pages(struct linux_binprm *bprm, int executable_stack);
#define VDSO_AUX_ENT(a,b) NEW_AUX_ENT(a,b);
#else
#define VDSO_AUX_ENT(a,b)
#endif /* __powerpc64__ */

/*
 * The requirements here are:
 * - keep the final alignment of sp (sp & 0xf)
 * - make sure the 32-bit value at the first 16 byte aligned position of
 *   AUXV is greater than 16 for glibc compatibility.
 *   AT_IGNOREPPC is used for that.
 * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
 *   even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
 */
#define ARCH_DLINFO							\
do {									\
	/* Handle glibc compatibility. */				\
	NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC);			\
	NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC);			\
	/* Cache size items */						\
	NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize);			\
	NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize);			\
	NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize);			\
	VDSO_AUX_ENT(AT_SYSINFO_EHDR, current->thread.vdso_base)	\
} while (0)

/* PowerPC64 relocations defined by the ABIs */
#define R_PPC64_NONE    R_PPC_NONE
#define R_PPC64_ADDR32  R_PPC_ADDR32  /* 32bit absolute address.  */
#define R_PPC64_ADDR24  R_PPC_ADDR24  /* 26bit address, word aligned.  */
#define R_PPC64_ADDR16  R_PPC_ADDR16  /* 16bit absolute address. */
#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of abs. address.  */
#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of abs. address. */
#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits.  */
#define R_PPC64_ADDR14 R_PPC_ADDR14   /* 16bit address, word aligned.  */
#define R_PPC64_ADDR14_BRTAKEN  R_PPC_ADDR14_BRTAKEN
#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN
#define R_PPC64_REL24   R_PPC_REL24 /* PC relative 26 bit, word aligned.  */
#define R_PPC64_REL14   R_PPC_REL14 /* PC relative 16 bit. */
#define R_PPC64_REL14_BRTAKEN   R_PPC_REL14_BRTAKEN
#define R_PPC64_REL14_BRNTAKEN  R_PPC_REL14_BRNTAKEN
#define R_PPC64_GOT16     R_PPC_GOT16
#define R_PPC64_GOT16_LO  R_PPC_GOT16_LO
#define R_PPC64_GOT16_HI  R_PPC_GOT16_HI
#define R_PPC64_GOT16_HA  R_PPC_GOT16_HA

#define R_PPC64_COPY      R_PPC_COPY
#define R_PPC64_GLOB_DAT  R_PPC_GLOB_DAT
#define R_PPC64_JMP_SLOT  R_PPC_JMP_SLOT
#define R_PPC64_RELATIVE  R_PPC_RELATIVE

#define R_PPC64_UADDR32   R_PPC_UADDR32
#define R_PPC64_UADDR16   R_PPC_UADDR16
#define R_PPC64_REL32     R_PPC_REL32
#define R_PPC64_PLT32     R_PPC_PLT32
#define R_PPC64_PLTREL32  R_PPC_PLTREL32
#define R_PPC64_PLT16_LO  R_PPC_PLT16_LO
#define R_PPC64_PLT16_HI  R_PPC_PLT16_HI
#define R_PPC64_PLT16_HA  R_PPC_PLT16_HA

#define R_PPC64_SECTOFF     R_PPC_SECTOFF
#define R_PPC64_SECTOFF_LO  R_PPC_SECTOFF_LO
#define R_PPC64_SECTOFF_HI  R_PPC_SECTOFF_HI
#define R_PPC64_SECTOFF_HA  R_PPC_SECTOFF_HA
#define R_PPC64_ADDR30          37  /* word30 (S + A - P) >> 2.  */
#define R_PPC64_ADDR64          38  /* doubleword64 S + A.  */
#define R_PPC64_ADDR16_HIGHER   39  /* half16 #higher(S + A).  */
#define R_PPC64_ADDR16_HIGHERA  40  /* half16 #highera(S + A).  */
#define R_PPC64_ADDR16_HIGHEST  41  /* half16 #highest(S + A).  */
#define R_PPC64_ADDR16_HIGHESTA 42  /* half16 #highesta(S + A). */
#define R_PPC64_UADDR64     43  /* doubleword64 S + A.  */
#define R_PPC64_REL64       44  /* doubleword64 S + A - P.  */
#define R_PPC64_PLT64       45  /* doubleword64 L + A.  */
#define R_PPC64_PLTREL64    46  /* doubleword64 L + A - P.  */
#define R_PPC64_TOC16       47  /* half16* S + A - .TOC.  */
#define R_PPC64_TOC16_LO    48  /* half16 #lo(S + A - .TOC.).  */
#define R_PPC64_TOC16_HI    49  /* half16 #hi(S + A - .TOC.).  */
#define R_PPC64_TOC16_HA    50  /* half16 #ha(S + A - .TOC.).  */
#define R_PPC64_TOC         51  /* doubleword64 .TOC. */
#define R_PPC64_PLTGOT16    52  /* half16* M + A.  */
#define R_PPC64_PLTGOT16_LO 53  /* half16 #lo(M + A).  */
#define R_PPC64_PLTGOT16_HI 54  /* half16 #hi(M + A).  */
#define R_PPC64_PLTGOT16_HA 55  /* half16 #ha(M + A).  */

#define R_PPC64_ADDR16_DS      56 /* half16ds* (S + A) >> 2.  */
#define R_PPC64_ADDR16_LO_DS   57 /* half16ds  #lo(S + A) >> 2.  */
#define R_PPC64_GOT16_DS       58 /* half16ds* (G + A) >> 2.  */
#define R_PPC64_GOT16_LO_DS    59 /* half16ds  #lo(G + A) >> 2.  */
#define R_PPC64_PLT16_LO_DS    60 /* half16ds  #lo(L + A) >> 2.  */
#define R_PPC64_SECTOFF_DS     61 /* half16ds* (R + A) >> 2.  */
#define R_PPC64_SECTOFF_LO_DS  62 /* half16ds  #lo(R + A) >> 2.  */
#define R_PPC64_TOC16_DS       63 /* half16ds* (S + A - .TOC.) >> 2.  */
#define R_PPC64_TOC16_LO_DS    64 /* half16ds  #lo(S + A - .TOC.) >> 2.  */
#define R_PPC64_PLTGOT16_DS    65 /* half16ds* (M + A) >> 2.  */
#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds  #lo(M + A) >> 2.  */

/* PowerPC64 relocations defined for the TLS access ABI.  */
#define R_PPC64_TLS		67 /* none	(sym+add)@tls */
#define R_PPC64_DTPMOD64	68 /* doubleword64 (sym+add)@dtpmod */
#define R_PPC64_TPREL16		69 /* half16*	(sym+add)@tprel */
#define R_PPC64_TPREL16_LO	70 /* half16	(sym+add)@tprel@l */
#define R_PPC64_TPREL16_HI	71 /* half16	(sym+add)@tprel@h */
#define R_PPC64_TPREL16_HA	72 /* half16	(sym+add)@tprel@ha */
#define R_PPC64_TPREL64		73 /* doubleword64 (sym+add)@tprel */
#define R_PPC64_DTPREL16	74 /* half16*	(sym+add)@dtprel */
#define R_PPC64_DTPREL16_LO	75 /* half16	(sym+add)@dtprel@l */
#define R_PPC64_DTPREL16_HI	76 /* half16	(sym+add)@dtprel@h */
#define R_PPC64_DTPREL16_HA	77 /* half16	(sym+add)@dtprel@ha */
#define R_PPC64_DTPREL64	78 /* doubleword64 (sym+add)@dtprel */
#define R_PPC64_GOT_TLSGD16	79 /* half16*	(sym+add)@got@tlsgd */
#define R_PPC64_GOT_TLSGD16_LO	80 /* half16	(sym+add)@got@tlsgd@l */
#define R_PPC64_GOT_TLSGD16_HI	81 /* half16	(sym+add)@got@tlsgd@h */
#define R_PPC64_GOT_TLSGD16_HA	82 /* half16	(sym+add)@got@tlsgd@ha */
#define R_PPC64_GOT_TLSLD16	83 /* half16*	(sym+add)@got@tlsld */
#define R_PPC64_GOT_TLSLD16_LO	84 /* half16	(sym+add)@got@tlsld@l */
#define R_PPC64_GOT_TLSLD16_HI	85 /* half16	(sym+add)@got@tlsld@h */
#define R_PPC64_GOT_TLSLD16_HA	86 /* half16	(sym+add)@got@tlsld@ha */
#define R_PPC64_GOT_TPREL16_DS	87 /* half16ds*	(sym+add)@got@tprel */
#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */
#define R_PPC64_GOT_TPREL16_HI	89 /* half16	(sym+add)@got@tprel@h */
#define R_PPC64_GOT_TPREL16_HA	90 /* half16	(sym+add)@got@tprel@ha */
#define R_PPC64_GOT_DTPREL16_DS	91 /* half16ds*	(sym+add)@got@dtprel */
#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */
#define R_PPC64_GOT_DTPREL16_HI	93 /* half16	(sym+add)@got@dtprel@h */
#define R_PPC64_GOT_DTPREL16_HA	94 /* half16	(sym+add)@got@dtprel@ha */
#define R_PPC64_TPREL16_DS	95 /* half16ds*	(sym+add)@tprel */
#define R_PPC64_TPREL16_LO_DS	96 /* half16ds	(sym+add)@tprel@l */
#define R_PPC64_TPREL16_HIGHER	97 /* half16	(sym+add)@tprel@higher */
#define R_PPC64_TPREL16_HIGHERA	98 /* half16	(sym+add)@tprel@highera */
#define R_PPC64_TPREL16_HIGHEST	99 /* half16	(sym+add)@tprel@highest */
#define R_PPC64_TPREL16_HIGHESTA 100 /* half16	(sym+add)@tprel@highesta */
#define R_PPC64_DTPREL16_DS	101 /* half16ds* (sym+add)@dtprel */
#define R_PPC64_DTPREL16_LO_DS	102 /* half16ds	(sym+add)@dtprel@l */
#define R_PPC64_DTPREL16_HIGHER	103 /* half16	(sym+add)@dtprel@higher */
#define R_PPC64_DTPREL16_HIGHERA 104 /* half16	(sym+add)@dtprel@highera */
#define R_PPC64_DTPREL16_HIGHEST 105 /* half16	(sym+add)@dtprel@highest */
#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16	(sym+add)@dtprel@highesta */

/* Keep this the last entry.  */
#define R_PPC64_NUM		107

#endif /* _ASM_POWERPC_ELF_H */
/* arch/sparc64/kernel/traps.c
 *
 * Copyright (C) 1995,1997,2008,2009,2012 David S. Miller (davem@davemloft.net)
 * Copyright (C) 1997,1999,2000 Jakub Jelinek (jakub@redhat.com)
 */

/*
 * I like traps on v9, :))))
 */

#include <linux/module.h>
#include <linux/sched.h>
#include <linux/linkage.h>
#include <linux/kernel.h>
#include <linux/signal.h>
#include <linux/smp.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/kdebug.h>
#include <linux/ftrace.h>
#include <linux/reboot.h>
#include <linux/gfp.h>
#include <linux/context_tracking.h>

#include <asm/smp.h>
#include <asm/delay.h>
#include <asm/ptrace.h>
#include <asm/oplib.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/unistd.h>
#include <asm/uaccess.h>
#include <asm/fpumacro.h>
#include <asm/lsu.h>
#include <asm/dcu.h>
#include <asm/estate.h>
#include <asm/chafsr.h>
#include <asm/sfafsr.h>
#include <asm/psrcompat.h>
#include <asm/processor.h>
#include <asm/timer.h>
#include <asm/head.h>
#include <asm/prom.h>
#include <asm/memctrl.h>
#include <asm/cacheflush.h>
#include <asm/setup.h>

#include "entry.h"
#include "kernel.h"
#include "kstack.h"

/* When an irrecoverable trap occurs at tl > 0, the trap entry
 * code logs the trap state registers at every level in the trap
 * stack.  It is found at (pt_regs + sizeof(pt_regs)) and the layout
 * is as follows:
 */
struct tl1_traplog {
	struct {
		unsigned long tstate;
		unsigned long tpc;
		unsigned long tnpc;
		unsigned long tt;
	} trapstack[4];
	unsigned long tl;
};

static void dump_tl1_traplog(struct tl1_traplog *p)
{
	int i, limit;

	printk(KERN_EMERG "TRAPLOG: Error at trap level 0x%lx, "
	       "dumping track stack.\n", p->tl);

	limit = (tlb_type == hypervisor) ? 2 : 4;
	for (i = 0; i < limit; i++) {
		printk(KERN_EMERG
		       "TRAPLOG: Trap level %d TSTATE[%016lx] TPC[%016lx] "
		       "TNPC[%016lx] TT[%lx]\n",
		       i + 1,
		       p->trapstack[i].tstate, p->trapstack[i].tpc,
		       p->trapstack[i].tnpc, p->trapstack[i].tt);
		printk("TRAPLOG: TPC<%pS>\n", (void *) p->trapstack[i].tpc);
	}
}

void bad_trap(struct pt_regs *regs, long lvl)
{
	char buffer[32];
	siginfo_t info;

	if (notify_die(DIE_TRAP, "bad trap", regs,
		       0, lvl, SIGTRAP) == NOTIFY_STOP)
		return;

	if (lvl < 0x100) {
		sprintf(buffer, "Bad hw trap %lx at tl0\n", lvl);
		die_if_kernel(buffer, regs);
	}

	lvl -= 0x100;
	if (regs->tstate & TSTATE_PRIV) {
		sprintf(buffer, "Kernel bad sw trap %lx", lvl);
		die_if_kernel(buffer, regs);
	}
	if (test_thread_flag(TIF_32BIT)) {
		regs->tpc &= 0xffffffff;
		regs->tnpc &= 0xffffffff;
	}
	info.si_signo = SIGILL;
	info.si_errno = 0;
	info.si_code = ILL_ILLTRP;
	info.si_addr = (void __user *)regs->tpc;
	info.si_trapno = lvl;
	force_sig_info(SIGILL, &info, current);
}

void bad_trap_tl1(struct pt_regs *regs, long lvl)
{
	char buffer[32];
	
	if (notify_die(DIE_TRAP_TL1, "bad trap tl1", regs,
		       0, lvl, SIGTRAP) == NOTIFY_STOP)
		return;

	dump_tl1_traplog((struct tl1_traplog *)(regs + 1));

	sprintf (buffer, "Bad trap %lx at tl>0", lvl);
	die_if_kernel (buffer, regs);
}

#ifdef CONFIG_DEBUG_BUGVERBOSE
void do_BUG(const char *file, int line)
{
	bust_spinlocks(1);
	printk("kernel BUG at %s:%d!\n", file, line);
}
EXPORT_SYMBOL(do_BUG);
#endif

static DEFINE_SPINLOCK(dimm_handler_lock);
static dimm_printer_t dimm_handler;

static int sprintf_dimm(int synd_code, unsigned long paddr, char *buf, int buflen)
{
	unsigned long flags;
	int ret = -ENODEV;

	spin_lock_irqsave(&dimm_handler_lock, flags);
	if (dimm_handler) {
		ret = dimm_handler(synd_code, paddr, buf, buflen);
	} else if (tlb_type == spitfire) {
		if (prom_getunumber(synd_code, paddr, buf, buflen) == -1)
			ret = -EINVAL;
		else
			ret = 0;
	} else
		ret = -ENODEV;
	spin_unlock_irqrestore(&dimm_handler_lock, flags);

	return ret;
}

int register_dimm_printer(dimm_printer_t func)
{
	unsigned long flags;
	int ret = 0;

	spin_lock_irqsave(&dimm_handler_lock, flags);
	if (!dimm_handler)
		dimm_handler = func;
	else
		ret = -EEXIST;
	spin_unlock_irqrestore(&dimm_handler_lock, flags);

	return ret;
}
EXPORT_SYMBOL_GPL(register_dimm_printer);

void unregister_dimm_printer(dimm_printer_t func)
{
	unsigned long flags;

	spin_lock_irqsave(&dimm_handler_lock, flags);
	if (dimm_handler == func)
		dimm_handler = NULL;
	spin_unlock_irqrestore(&dimm_handler_lock, flags);
}
EXPORT_SYMBOL_GPL(unregister_dimm_printer);

void spitfire_insn_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
{
	enum ctx_state prev_state = exception_enter();
	siginfo_t info;

	if (notify_die(DIE_TRAP, "instruction access exception", regs,
		       0, 0x8, SIGTRAP) == NOTIFY_STOP)
		goto out;

	if (regs->tstate & TSTATE_PRIV) {
		printk("spitfire_insn_access_exception: SFSR[%016lx] "
		       "SFAR[%016lx], going.\n", sfsr, sfar);
		die_if_kernel("Iax", regs);
	}
	if (test_thread_flag(TIF_32BIT)) {
		regs->tpc &= 0xffffffff;
		regs->tnpc &= 0xffffffff;
	}
	info.si_signo = SIGSEGV;
	info.si_errno = 0;
	info.si_code = SEGV_MAPERR;
	info.si_addr = (void __user *)regs->tpc;
	info.si_trapno = 0;
	force_sig_info(SIGSEGV, &info, current);
out:
	exception_exit(prev_state);
}

void spitfire_insn_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
{
	if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
		       0, 0x8, SIGTRAP) == NOTIFY_STOP)
		return;

	dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
	spitfire_insn_access_exception(regs, sfsr, sfar);
}

void sun4v_insn_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
{
	unsigned short type = (type_ctx >> 16);
	unsigned short ctx  = (type_ctx & 0xffff);
	siginfo_t info;

	if (notify_die(DIE_TRAP, "instruction access exception", regs,
		       0, 0x8, SIGTRAP) == NOTIFY_STOP)
		return;

	if (regs->tstate & TSTATE_PRIV) {
		printk("sun4v_insn_access_exception: ADDR[%016lx] "
		       "CTX[%04x] TYPE[%04x], going.\n",
		       addr, ctx, type);
		die_if_kernel("Iax", regs);
	}

	if (test_thread_flag(TIF_32BIT)) {
		regs->tpc &= 0xffffffff;
		regs->tnpc &= 0xffffffff;
	}
	info.si_signo = SIGSEGV;
	info.si_errno = 0;
	info.si_code = SEGV_MAPERR;
	info.si_addr = (void __user *) addr;
	info.si_trapno = 0;
	force_sig_info(SIGSEGV, &info, current);
}

void sun4v_insn_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
{
	if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
		       0, 0x8, SIGTRAP) == NOTIFY_STOP)
		return;

	dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
	sun4v_insn_access_exception(regs, addr, type_ctx);
}

void spitfire_data_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
{
	enum ctx_state prev_state = exception_enter();
	siginfo_t info;

	if (notify_die(DIE_TRAP, "data access exception", regs,
		       0, 0x30, SIGTRAP) == NOTIFY_STOP)
		goto out;

	if (regs->tstate & TSTATE_PRIV) {
		/* Test if this comes from uaccess places. */
		const struct exception_table_entry *entry;

		entry = search_exception_tables(regs->tpc);
		if (entry) {
			/* Ouch, somebody is trying VM hole tricks on us... */
#ifdef DEBUG_EXCEPTIONS
			printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
			printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
			       regs->tpc, entry->fixup);
#endif
			regs->tpc = entry->fixup;
			regs->tnpc = regs->tpc + 4;
			goto out;
		}
		/* Shit... */
		printk("spitfire_data_access_exception: SFSR[%016lx] "
		       "SFAR[%016lx], going.\n", sfsr, sfar);
		die_if_kernel("Dax", regs);
	}

	info.si_signo = SIGSEGV;
	info.si_errno = 0;
	info.si_code = SEGV_MAPERR;
	info.si_addr = (void __user *)sfar;
	info.si_trapno = 0;
	force_sig_info(SIGSEGV, &info, current);
out:
	exception_exit(prev_state);
}

void spitfire_data_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
{
	if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
		       0, 0x30, SIGTRAP) == NOTIFY_STOP)
		return;

	dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
	spitfire_data_access_exception(regs, sfsr, sfar);
}

void sun4v_data_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
{
	unsigned short type = (type_ctx >> 16);
	unsigned short ctx  = (type_ctx & 0xffff);
	siginfo_t info;

	if (notify_die(DIE_TRAP, "data access exception", regs,
		       0, 0x8, SIGTRAP) == NOTIFY_STOP)
		return;

	if (regs->tstate & TSTATE_PRIV) {
		/* Test if this comes from uaccess places. */
		const struct exception_table_entry *entry;

		entry = search_exception_tables(regs->tpc);
		if (entry) {
			/* Ouch, somebody is trying VM hole tricks on us... */
#ifdef DEBUG_EXCEPTIONS
			printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
			printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
			       regs->tpc, entry->fixup);
#endif
			regs->tpc = entry->fixup;
			regs->tnpc = regs->tpc + 4;
			return;
		}
		printk("sun4v_data_access_exception: ADDR[%016lx] "
		       "CTX[%04x] TYPE[%04x], going.\n",
		       addr, ctx, type);
		die_if_kernel("Dax", regs);
	}

	if (test_thread_flag(TIF_32BIT)) {
		regs->tpc &= 0xffffffff;
		regs->tnpc &= 0xffffffff;
	}
	info.si_signo = SIGSEGV;
	info.si_errno = 0;
	info.si_code = SEGV_MAPERR;
	info.si_addr = (void __user *) addr;
	info.si_trapno = 0;
	force_sig_info(SIGSEGV, &info, current);
}

void sun4v_data_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
{
	if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
		       0, 0x8, SIGTRAP) == NOTIFY_STOP)
		return;

	dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
	sun4v_data_access_exception(regs, addr, type_ctx);
}

#ifdef CONFIG_PCI
#include "pci_impl.h"
#endif

/* When access exceptions happen, we must do this. */
static void spitfire_clean_and_reenable_l1_caches(void)
{
	unsigned long va;

	if (tlb_type != spitfire)
		BUG();

	/* Clean 'em. */
	for (va =  0; va < (PAGE_SIZE << 1); va += 32) {
		spitfire_put_icache_tag(va, 0x0);
		spitfire_put_dcache_tag(va, 0x0);
	}

	/* Re-enable in LSU. */
	__asm__ __volatile__("flush %%g6\n\t"
			     "membar #Sync\n\t"
			     "stxa %0, [%%g0] %1\n\t"
			     "membar #Sync"
			     : /* no outputs */
			     : "r" (LSU_CONTROL_IC | LSU_CONTROL_DC |
				    LSU_CONTROL_IM | LSU_CONTROL_DM),
			     "i" (ASI_LSU_CONTROL)
			     : "memory");
}

static void spitfire_enable_estate_errors(void)
{
	__asm__ __volatile__("stxa	%0, [%%g0] %1\n\t"
			     "membar	#Sync"
			     : /* no outputs */
			     : "r" (ESTATE_ERR_ALL),
			       "i" (ASI_ESTATE_ERROR_EN));
}

static char ecc_syndrome_table[] = {
	0x4c, 0x40, 0x41, 0x48, 0x42, 0x48, 0x48, 0x49,
	0x43, 0x48, 0x48, 0x49, 0x48, 0x49, 0x49, 0x4a,
	0x44, 0x48, 0x48, 0x20, 0x48, 0x39, 0x4b, 0x48,
	0x48, 0x25, 0x31, 0x48, 0x28, 0x48, 0x48, 0x2c,
	0x45, 0x48, 0x48, 0x21, 0x48, 0x3d, 0x04, 0x48,
	0x48, 0x4b, 0x35, 0x48, 0x2d, 0x48, 0x48, 0x29,
	0x48, 0x00, 0x01, 0x48, 0x0a, 0x48, 0x48, 0x4b,
	0x0f, 0x48, 0x48, 0x4b, 0x48, 0x49, 0x49, 0x48,
	0x46, 0x48, 0x48, 0x2a, 0x48, 0x3b, 0x27, 0x48,
	0x48, 0x4b, 0x33, 0x48, 0x22, 0x48, 0x48, 0x2e,
	0x48, 0x19, 0x1d, 0x48, 0x1b, 0x4a, 0x48, 0x4b,
	0x1f, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
	0x48, 0x4b, 0x24, 0x48, 0x07, 0x48, 0x48, 0x36,
	0x4b, 0x48, 0x48, 0x3e, 0x48, 0x30, 0x38, 0x48,
	0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x16, 0x48,
	0x48, 0x12, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
	0x47, 0x48, 0x48, 0x2f, 0x48, 0x3f, 0x4b, 0x48,
	0x48, 0x06, 0x37, 0x48, 0x23, 0x48, 0x48, 0x2b,
	0x48, 0x05, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x32,
	0x26, 0x48, 0x48, 0x3a, 0x48, 0x34, 0x3c, 0x48,
	0x48, 0x11, 0x15, 0x48, 0x13, 0x4a, 0x48, 0x4b,
	0x17, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
	0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x1e, 0x48,
	0x48, 0x1a, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
	0x48, 0x08, 0x0d, 0x48, 0x02, 0x48, 0x48, 0x49,
	0x03, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x4b, 0x48,
	0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x10, 0x48,
	0x48, 0x14, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
	0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x18, 0x48,
	0x48, 0x1c, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
	0x4a, 0x0c, 0x09, 0x48, 0x0e, 0x48, 0x48, 0x4b,
	0x0b, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x4b, 0x4a
};

static char *syndrome_unknown = "<Unknown>";

static void spitfire_log_udb_syndrome(unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long bit)
{
	unsigned short scode;
	char memmod_str[64], *p;

	if (udbl & bit) {
		scode = ecc_syndrome_table[udbl & 0xff];
		if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0)
			p = syndrome_unknown;
		else
			p = memmod_str;
		printk(KERN_WARNING "CPU[%d]: UDBL Syndrome[%x] "
		       "Memory Module \"%s\"\n",
		       smp_processor_id(), scode, p);
	}

	if (udbh & bit) {
		scode = ecc_syndrome_table[udbh & 0xff];
		if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0)
			p = syndrome_unknown;
		else
			p = memmod_str;
		printk(KERN_WARNING "CPU[%d]: UDBH Syndrome[%x] "
		       "Memory Module \"%s\"\n",
		       smp_processor_id(), scode, p);
	}

}

static void spitfire_cee_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, int tl1, struct pt_regs *regs)
{

	printk(KERN_WARNING "CPU[%d]: Correctable ECC Error "
	       "AFSR[%lx] AFAR[%016lx] UDBL[%lx] UDBH[%lx] TL>1[%d]\n",
	       smp_processor_id(), afsr, afar, udbl, udbh, tl1);

	spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_CE);

	/* We always log it, even if someone is listening for this
	 * trap.
	 */
	notify_die(DIE_TRAP, "Correctable ECC Error", regs,
		   0, TRAP_TYPE_CEE, SIGTRAP);

	/* The Correctable ECC Error trap does not disable I/D caches.  So
	 * we only have to restore the ESTATE Error Enable register.
	 */
	spitfire_enable_estate_errors();
}

static void spitfire_ue_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long tt, int tl1, struct pt_regs *regs)
{
	siginfo_t info;

	printk(KERN_WARNING "CPU[%d]: Uncorrectable Error AFSR[%lx] "
	       "AFAR[%lx] UDBL[%lx] UDBH[%ld] TT[%lx] TL>1[%d]\n",
	       smp_processor_id(), afsr, afar, udbl, udbh, tt, tl1);

	/* XXX add more human friendly logging of the error status
	 * XXX as is implemented for cheetah
	 */

	spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_UE);

	/* We always log it, even if someone is listening for this
	 * trap.
	 */
	notify_die(DIE_TRAP, "Uncorrectable Error", regs,
		   0, tt, SIGTRAP);

	if (regs->tstate & TSTATE_PRIV) {
		if (tl1)
			dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
		die_if_kernel("UE", regs);
	}

	/* XXX need more intelligent processing here, such as is implemented
	 * XXX for cheetah errors, in fact if the E-cache still holds the
	 * XXX line with bad parity this will loop
	 */

	spitfire_clean_and_reenable_l1_caches();
	spitfire_enable_estate_errors();

	if (test_thread_flag(TIF_32BIT)) {
		regs->tpc &= 0xffffffff;
		regs->tnpc &= 0xffffffff;
	}
	info.si_signo = SIGBUS;
	info.si_errno = 0;
	info.si_code = BUS_OBJERR;
	info.si_addr = (void *)0;
	info.si_trapno = 0;
	force_sig_info(SIGBUS, &info, current);
}

void spitfire_access_error(struct pt_regs *regs, unsigned long status_encoded, unsigned long afar)
{
	unsigned long afsr, tt, udbh, udbl;
	int tl1;

	afsr = (status_encoded & SFSTAT_AFSR_MASK) >> SFSTAT_AFSR_SHIFT;
	tt = (status_encoded & SFSTAT_TRAP_TYPE) >> SFSTAT_TRAP_TYPE_SHIFT;
	tl1 = (status_encoded & SFSTAT_TL_GT_ONE) ? 1 : 0;
	udbl = (status_encoded & SFSTAT_UDBL_MASK) >> SFSTAT_UDBL_SHIFT;
	udbh = (status_encoded & SFSTAT_UDBH_MASK) >> SFSTAT_UDBH_SHIFT;

#ifdef CONFIG_PCI
	if (tt == TRAP_TYPE_DAE &&
	    pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
		spitfire_clean_and_reenable_l1_caches();
		spitfire_enable_estate_errors();

		pci_poke_faulted = 1;
		regs->tnpc = regs->tpc + 4;
		return;
	}
#endif

	if (afsr & SFAFSR_UE)
		spitfire_ue_log(afsr, afar, udbh, udbl, tt, tl1, regs);

	if (tt == TRAP_TYPE_CEE) {
		/* Handle the case where we took a CEE trap, but ACK'd
		 * only the UE state in the UDB error registers.
		 */
		if (afsr & SFAFSR_UE) {
			if (udbh & UDBE_CE) {
				__asm__ __volatile__(
					"stxa	%0, [%1] %2\n\t"
					"membar	#Sync"
					: /* no outputs */
					: "r" (udbh & UDBE_CE),
					  "r" (0x0), "i" (ASI_UDB_ERROR_W));
			}
			if (udbl & UDBE_CE) {
				__asm__ __volatile__(
					"stxa	%0, [%1] %2\n\t"
					"membar	#Sync"
					: /* no outputs */
					: "r" (udbl & UDBE_CE),
					  "r" (0x18), "i" (ASI_UDB_ERROR_W));
			}
		}

		spitfire_cee_log(afsr, afar, udbh, udbl, tl1, regs);
	}
}

int cheetah_pcache_forced_on;

void cheetah_enable_pcache(void)
{
	unsigned long dcr;

	printk("CHEETAH: Enabling P-Cache on cpu %d.\n",
	       smp_processor_id());

	__asm__ __volatile__("ldxa [%%g0] %1, %0"
			     : "=r" (dcr)
			     : "i" (ASI_DCU_CONTROL_REG));
	dcr |= (DCU_PE | DCU_HPE | DCU_SPE | DCU_SL);
	__asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
			     "membar #Sync"
			     : /* no outputs */
			     : "r" (dcr), "i" (ASI_DCU_CONTROL_REG));
}

/* Cheetah error trap handling. */
static unsigned long ecache_flush_physbase;
static unsigned long ecache_flush_linesize;
static unsigned long ecache_flush_size;

/* This table is ordered in priority of errors and matches the
 * AFAR overwrite policy as well.
 */

struct afsr_error_table {
	unsigned long mask;
	const char *name;
};

static const char CHAFSR_PERR_msg[] =
	"System interface protocol error";
static const char CHAFSR_IERR_msg[] =
	"Internal processor error";
static const char CHAFSR_ISAP_msg[] =
	"System request parity error on incoming address";
static const char CHAFSR_UCU_msg[] =
	"Uncorrectable E-cache ECC error for ifetch/data";
static const char CHAFSR_UCC_msg[] =
	"SW Correctable E-cache ECC error for ifetch/data";
static const char CHAFSR_UE_msg[] =
	"Uncorrectable system bus data ECC error for read";
static const char CHAFSR_EDU_msg[] =
	"Uncorrectable E-cache ECC error for stmerge/blkld";
static const char CHAFSR_EMU_msg[] =
	"Uncorrectable system bus MTAG error";
static const char CHAFSR_WDU_msg[] =
	"Uncorrectable E-cache ECC error for writeback";
static const char CHAFSR_CPU_msg[] =
	"Uncorrectable ECC error for copyout";
static const char CHAFSR_CE_msg[] =
	"HW corrected system bus data ECC error for read";
static const char CHAFSR_EDC_msg[] =
	"HW corrected E-cache ECC error for stmerge/blkld";
static const char CHAFSR_EMC_msg[] =
	"HW corrected system bus MTAG ECC error";
static const char CHAFSR_WDC_msg[] =
	"HW corrected E-cache ECC error for writeback";
static const char CHAFSR_CPC_msg[] =
	"HW corrected ECC error for copyout";
static const char CHAFSR_TO_msg[] =
	"Unmapped error from system bus";
static const char CHAFSR_BERR_msg[] =
	"Bus error response from system bus";
static const char CHAFSR_IVC_msg[] =
	"HW corrected system bus data ECC error for ivec read";
static const char CHAFSR_IVU_msg[] =
	"Uncorrectable system bus data ECC error for ivec read";
static struct afsr_error_table __cheetah_error_table[] = {
	{	CHAFSR_PERR,	CHAFSR_PERR_msg		},
	{	CHAFSR_IERR,	CHAFSR_IERR_msg		},
	{	CHAFSR_ISAP,	CHAFSR_ISAP_msg		},
	{	CHAFSR_UCU,	CHAFSR_UCU_msg		},
	{	CHAFSR_UCC,	CHAFSR_UCC_msg		},
	{	CHAFSR_UE,	CHAFSR_UE_msg		},
	{	CHAFSR_EDU,	CHAFSR_EDU_msg		},
	{	CHAFSR_EMU,	CHAFSR_EMU_msg		},
	{	CHAFSR_WDU,	CHAFSR_WDU_msg		},
	{	CHAFSR_CPU,	CHAFSR_CPU_msg		},
	{	CHAFSR_CE,	CHAFSR_CE_msg		},
	{	CHAFSR_EDC,	CHAFSR_EDC_msg		},
	{	CHAFSR_EMC,	CHAFSR_EMC_msg		},
	{	CHAFSR_WDC,	CHAFSR_WDC_msg		},
	{	CHAFSR_CPC,	CHAFSR_CPC_msg		},
	{	CHAFSR_TO,	CHAFSR_TO_msg		},
	{	CHAFSR_BERR,	CHAFSR_BERR_msg		},
	/* These two do not update the AFAR. */
	{	CHAFSR_IVC,	CHAFSR_IVC_msg		},
	{	CHAFSR_IVU,	CHAFSR_IVU_msg		},
	{	0,		NULL			},
};
static const char CHPAFSR_DTO_msg[] =
	"System bus unmapped error for prefetch/storequeue-read";
static const char CHPAFSR_DBERR_msg[] =
	"System bus error for prefetch/storequeue-read";
static const char CHPAFSR_THCE_msg[] =
	"Hardware corrected E-cache Tag ECC error";
static const char CHPAFSR_TSCE_msg[] =
	"SW handled correctable E-cache Tag ECC error";
static const char CHPAFSR_TUE_msg[] =
	"Uncorrectable E-cache Tag ECC error";
static const char CHPAFSR_DUE_msg[] =
	"System bus uncorrectable data ECC error due to prefetch/store-fill";
static struct afsr_error_table __cheetah_plus_error_table[] = {
	{	CHAFSR_PERR,	CHAFSR_PERR_msg		},
	{	CHAFSR_IERR,	CHAFSR_IERR_msg		},
	{	CHAFSR_ISAP,	CHAFSR_ISAP_msg		},
	{	CHAFSR_UCU,	CHAFSR_UCU_msg		},
	{	CHAFSR_UCC,	CHAFSR_UCC_msg		},
	{	CHAFSR_UE,	CHAFSR_UE_msg		},
	{	CHAFSR_EDU,	CHAFSR_EDU_msg		},
	{	CHAFSR_EMU,	CHAFSR_EMU_msg		},
	{	CHAFSR_WDU,	CHAFSR_WDU_msg		},
	{	CHAFSR_CPU,	CHAFSR_CPU_msg		},
	{	CHAFSR_CE,	CHAFSR_CE_msg		},
	{	CHAFSR_EDC,	CHAFSR_EDC_msg		},
	{	CHAFSR_EMC,	CHAFSR_EMC_msg		},
	{	CHAFSR_WDC,	CHAFSR_WDC_msg		},
	{	CHAFSR_CPC,	CHAFSR_CPC_msg		},
	{	CHAFSR_TO,	CHAFSR_TO_msg		},
	{	CHAFSR_BERR,	CHAFSR_BERR_msg		},
	{	CHPAFSR_DTO,	CHPAFSR_DTO_msg		},
	{	CHPAFSR_DBERR,	CHPAFSR_DBERR_msg	},
	{	CHPAFSR_THCE,	CHPAFSR_THCE_msg	},
	{	CHPAFSR_TSCE,	CHPAFSR_TSCE_msg	},
	{	CHPAFSR_TUE,	CHPAFSR_TUE_msg		},
	{	CHPAFSR_DUE,	CHPAFSR_DUE_msg		},
	/* These two do not update the AFAR. */
	{	CHAFSR_IVC,	CHAFSR_IVC_msg		},
	{	CHAFSR_IVU,	CHAFSR_IVU_msg		},
	{	0,		NULL			},
};
static const char JPAFSR_JETO_msg[] =
	"System interface protocol error, hw timeout caused";
static const char JPAFSR_SCE_msg[] =
	"Parity error on system snoop results";
static const char JPAFSR_JEIC_msg[] =
	"System interface protocol error, illegal command detected";
static const char JPAFSR_JEIT_msg[] =
	"System interface protocol error, illegal ADTYPE detected";
static const char JPAFSR_OM_msg[] =
	"Out of range memory error has occurred";
static const char JPAFSR_ETP_msg[] =
	"Parity error on L2 cache tag SRAM";
static const char JPAFSR_UMS_msg[] =
	"Error due to unsupported store";
static const char JPAFSR_RUE_msg[] =
	"Uncorrectable ECC error from remote cache/memory";
static const char JPAFSR_RCE_msg[] =
	"Correctable ECC error from remote cache/memory";
static const char JPAFSR_BP_msg[] =
	"JBUS parity error on returned read data";
static const char JPAFSR_WBP_msg[] =
	"JBUS parity error on data for writeback or block store";
static const char JPAFSR_FRC_msg[] =
	"Foreign read to DRAM incurring correctable ECC error";
static const char JPAFSR_FRU_msg[] =
	"Foreign read to DRAM incurring uncorrectable ECC error";
static struct afsr_error_table __jalapeno_error_table[] = {
	{	JPAFSR_JETO,	JPAFSR_JETO_msg		},
	{	JPAFSR_SCE,	JPAFSR_SCE_msg		},
	{	JPAFSR_JEIC,	JPAFSR_JEIC_msg		},
	{	JPAFSR_JEIT,	JPAFSR_JEIT_msg		},
	{	CHAFSR_PERR,	CHAFSR_PERR_msg		},
	{	CHAFSR_IERR,	CHAFSR_IERR_msg		},
	{	CHAFSR_ISAP,	CHAFSR_ISAP_msg		},
	{	CHAFSR_UCU,	CHAFSR_UCU_msg		},
	{	CHAFSR_UCC,	CHAFSR_UCC_msg		},
	{	CHAFSR_UE,	CHAFSR_UE_msg		},
	{	CHAFSR_EDU,	CHAFSR_EDU_msg		},
	{	JPAFSR_OM,	JPAFSR_OM_msg		},
	{	CHAFSR_WDU,	CHAFSR_WDU_msg		},
	{	CHAFSR_CPU,	CHAFSR_CPU_msg		},
	{	CHAFSR_CE,	CHAFSR_CE_msg		},
	{	CHAFSR_EDC,	CHAFSR_EDC_msg		},
	{	JPAFSR_ETP,	JPAFSR_ETP_msg		},
	{	CHAFSR_WDC,	CHAFSR_WDC_msg		},
	{	CHAFSR_CPC,	CHAFSR_CPC_msg		},
	{	CHAFSR_TO,	CHAFSR_TO_msg		},
	{	CHAFSR_BERR,	CHAFSR_BERR_msg		},
	{	JPAFSR_UMS,	JPAFSR_UMS_msg		},
	{	JPAFSR_RUE,	JPAFSR_RUE_msg		},
	{	JPAFSR_RCE,	JPAFSR_RCE_msg		},
	{	JPAFSR_BP,	JPAFSR_BP_msg		},
	{	JPAFSR_WBP,	JPAFSR_WBP_msg		},
	{	JPAFSR_FRC,	JPAFSR_FRC_msg		},
	{	JPAFSR_FRU,	JPAFSR_FRU_msg		},
	/* These two do not update the AFAR. */
	{	CHAFSR_IVU,	CHAFSR_IVU_msg		},
	{	0,		NULL			},
};
static struct afsr_error_table *cheetah_error_table;
static unsigned long cheetah_afsr_errors;

struct cheetah_err_info *cheetah_error_log;

static inline struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
{
	struct cheetah_err_info *p;
	int cpu = smp_processor_id();

	if (!cheetah_error_log)
		return NULL;

	p = cheetah_error_log + (cpu * 2);
	if ((afsr & CHAFSR_TL1) != 0UL)
		p++;

	return p;
}

extern unsigned int tl0_icpe[], tl1_icpe[];
extern unsigned int tl0_dcpe[], tl1_dcpe[];
extern unsigned int tl0_fecc[], tl1_fecc[];
extern unsigned int tl0_cee[], tl1_cee[];
extern unsigned int tl0_iae[], tl1_iae[];
extern unsigned int tl0_dae[], tl1_dae[];
extern unsigned int cheetah_plus_icpe_trap_vector[], cheetah_plus_icpe_trap_vector_tl1[];
extern unsigned int cheetah_plus_dcpe_trap_vector[], cheetah_plus_dcpe_trap_vector_tl1[];
extern unsigned int cheetah_fecc_trap_vector[], cheetah_fecc_trap_vector_tl1[];
extern unsigned int cheetah_cee_trap_vector[], cheetah_cee_trap_vector_tl1[];
extern unsigned int cheetah_deferred_trap_vector[], cheetah_deferred_trap_vector_tl1[];

void __init cheetah_ecache_flush_init(void)
{
	unsigned long largest_size, smallest_linesize, order, ver;
	int i, sz;

	/* Scan all cpu device tree nodes, note two values:
	 * 1) largest E-cache size
	 * 2) smallest E-cache line size
	 */
	largest_size = 0UL;
	smallest_linesize = ~0UL;

	for (i = 0; i < NR_CPUS; i++) {
		unsigned long val;

		val = cpu_data(i).ecache_size;
		if (!val)
			continue;

		if (val > largest_size)
			largest_size = val;

		val = cpu_data(i).ecache_line_size;
		if (val < smallest_linesize)
			smallest_linesize = val;

	}

	if (largest_size == 0UL || smallest_linesize == ~0UL) {
		prom_printf("cheetah_ecache_flush_init: Cannot probe cpu E-cache "
			    "parameters.\n");
		prom_halt();
	}

	ecache_flush_size = (2 * largest_size);
	ecache_flush_linesize = smallest_linesize;

	ecache_flush_physbase = find_ecache_flush_span(ecache_flush_size);

	if (ecache_flush_physbase == ~0UL) {
		prom_printf("cheetah_ecache_flush_init: Cannot find %ld byte "
			    "contiguous physical memory.\n",
			    ecache_flush_size);
		prom_halt();
	}

	/* Now allocate error trap reporting scoreboard. */
	sz = NR_CPUS * (2 * sizeof(struct cheetah_err_info));
	for (order = 0; order < MAX_ORDER; order++) {
		if ((PAGE_SIZE << order) >= sz)
			break;
	}
	cheetah_error_log = (struct cheetah_err_info *)
		__get_free_pages(GFP_KERNEL, order);
	if (!cheetah_error_log) {
		prom_printf("cheetah_ecache_flush_init: Failed to allocate "
			    "error logging scoreboard (%d bytes).\n", sz);
		prom_halt();
	}
	memset(cheetah_error_log, 0, PAGE_SIZE << order);

	/* Mark all AFSRs as invalid so that the trap handler will
	 * log new new information there.
	 */
	for (i = 0; i < 2 * NR_CPUS; i++)
		cheetah_error_log[i].afsr = CHAFSR_INVALID;

	__asm__ ("rdpr %%ver, %0" : "=r" (ver));
	if ((ver >> 32) == __JALAPENO_ID ||
	    (ver >> 32) == __SERRANO_ID) {
		cheetah_error_table = &__jalapeno_error_table[0];
		cheetah_afsr_errors = JPAFSR_ERRORS;
	} else if ((ver >> 32) == 0x003e0015) {
		cheetah_error_table = &__cheetah_plus_error_table[0];
		cheetah_afsr_errors = CHPAFSR_ERRORS;
	} else {
		cheetah_error_table = &__cheetah_error_table[0];
		cheetah_afsr_errors = CHAFSR_ERRORS;
	}

	/* Now patch trap tables. */
	memcpy(tl0_fecc, cheetah_fecc_trap_vector, (8 * 4));
	memcpy(tl1_fecc, cheetah_fecc_trap_vector_tl1, (8 * 4));
	memcpy(tl0_cee, cheetah_cee_trap_vector, (8 * 4));
	memcpy(tl1_cee, cheetah_cee_trap_vector_tl1, (8 * 4));
	memcpy(tl0_iae, cheetah_deferred_trap_vector, (8 * 4));
	memcpy(tl1_iae, cheetah_deferred_trap_vector_tl1, (8 * 4));
	memcpy(tl0_dae, cheetah_deferred_trap_vector, (8 * 4));
	memcpy(tl1_dae, cheetah_deferred_trap_vector_tl1, (8 * 4));
	if (tlb_type == cheetah_plus) {
		memcpy(tl0_dcpe, cheetah_plus_dcpe_trap_vector, (8 * 4));
		memcpy(tl1_dcpe, cheetah_plus_dcpe_trap_vector_tl1, (8 * 4));
		memcpy(tl0_icpe, cheetah_plus_icpe_trap_vector, (8 * 4));
		memcpy(tl1_icpe, cheetah_plus_icpe_trap_vector_tl1, (8 * 4));
	}
	flushi(PAGE_OFFSET);
}

static void cheetah_flush_ecache(void)
{
	unsigned long flush_base = ecache_flush_physbase;
	unsigned long flush_linesize = ecache_flush_linesize;
	unsigned long flush_size = ecache_flush_size;

	__asm__ __volatile__("1: subcc	%0, %4, %0\n\t"
			     "   bne,pt	%%xcc, 1b\n\t"
			     "    ldxa	[%2 + %0] %3, %%g0\n\t"
			     : "=&r" (flush_size)
			     : "0" (flush_size), "r" (flush_base),
			       "i" (ASI_PHYS_USE_EC), "r" (flush_linesize));
}

static void cheetah_flush_ecache_line(unsigned long physaddr)
{
	unsigned long alias;

	physaddr &= ~(8UL - 1UL);
	physaddr = (ecache_flush_physbase +
		    (physaddr & ((ecache_flush_size>>1UL) - 1UL)));
	alias = physaddr + (ecache_flush_size >> 1UL);
	__asm__ __volatile__("ldxa [%0] %2, %%g0\n\t"
			     "ldxa [%1] %2, %%g0\n\t"
			     "membar #Sync"
			     : /* no outputs */
			     : "r" (physaddr), "r" (alias),
			       "i" (ASI_PHYS_USE_EC));
}

/* Unfortunately, the diagnostic access to the I-cache tags we need to
 * use to clear the thing interferes with I-cache coherency transactions.
 *
 * So we must only flush the I-cache when it is disabled.
 */
static void __cheetah_flush_icache(void)
{
	unsigned int icache_size, icache_line_size;
	unsigned long addr;

	icache_size = local_cpu_data().icache_size;
	icache_line_size = local_cpu_data().icache_line_size;

	/* Clear the valid bits in all the tags. */
	for (addr = 0; addr < icache_size; addr += icache_line_size) {
		__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
				     "membar #Sync"
				     : /* no outputs */
				     : "r" (addr | (2 << 3)),
				       "i" (ASI_IC_TAG));
	}
}

static void cheetah_flush_icache(void)
{
	unsigned long dcu_save;

	/* Save current DCU, disable I-cache. */
	__asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
			     "or %0, %2, %%g1\n\t"
			     "stxa %%g1, [%%g0] %1\n\t"
			     "membar #Sync"
			     : "=r" (dcu_save)
			     : "i" (ASI_DCU_CONTROL_REG), "i" (DCU_IC)
			     : "g1");

	__cheetah_flush_icache();

	/* Restore DCU register */
	__asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
			     "membar #Sync"
			     : /* no outputs */
			     : "r" (dcu_save), "i" (ASI_DCU_CONTROL_REG));
}

static void cheetah_flush_dcache(void)
{
	unsigned int dcache_size, dcache_line_size;
	unsigned long addr;

	dcache_size = local_cpu_data().dcache_size;
	dcache_line_size = local_cpu_data().dcache_line_size;

	for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
		__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
				     "membar #Sync"
				     : /* no outputs */
				     : "r" (addr), "i" (ASI_DCACHE_TAG));
	}
}

/* In order to make the even parity correct we must do two things.
 * First, we clear DC_data_parity and set DC_utag to an appropriate value.
 * Next, we clear out all 32-bytes of data for that line.  Data of
 * all-zero + tag parity value of zero == correct parity.
 */
static void cheetah_plus_zap_dcache_parity(void)
{
	unsigned int dcache_size, dcache_line_size;
	unsigned long addr;

	dcache_size = local_cpu_data().dcache_size;
	dcache_line_size = local_cpu_data().dcache_line_size;

	for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
		unsigned long tag = (addr >> 14);
		unsigned long line;

		__asm__ __volatile__("membar	#Sync\n\t"
				     "stxa	%0, [%1] %2\n\t"
				     "membar	#Sync"
				     : /* no outputs */
				     : "r" (tag), "r" (addr),
				       "i" (ASI_DCACHE_UTAG));
		for (line = addr; line < addr + dcache_line_size; line += 8)
			__asm__ __volatile__("membar	#Sync\n\t"
					     "stxa	%%g0, [%0] %1\n\t"
					     "membar	#Sync"
					     : /* no outputs */
					     : "r" (line),
					       "i" (ASI_DCACHE_DATA));
	}
}

/* Conversion tables used to frob Cheetah AFSR syndrome values into
 * something palatable to the memory controller driver get_unumber
 * routine.
 */
#define MT0	137
#define MT1	138
#define MT2	139
#define NONE	254
#define MTC0	140
#define MTC1	141
#define MTC2	142
#define MTC3	143
#define C0	128
#define C1	129
#define C2	130
#define C3	131
#define C4	132
#define C5	133
#define C6	134
#define C7	135
#define C8	136
#define M2	144
#define M3	145
#define M4	146
#define M	147
static unsigned char cheetah_ecc_syntab[] = {
/*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
/*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 11, M, M2, 16,
/*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
/*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
/*04*/C6, M, M, 43, M, 36, 18, M, M2, 49, 15, M, 63, M2, M2, 6,
/*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
/*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
/*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
/*08*/C7, M2, M, 42, M, 35, 17, M2, M, 45, 14, M2, 21, M2, M2, 5,
/*09*/M, 27, M, M, 99, M, M, 3, 114, M2, M2, 20, M2, M3, M3, M,
/*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
/*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
/*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
/*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
/*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M,
/*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M,
/*10*/C8, M, M2, 39, M, 34, 105, M2, M, 30, 104, M, 101, M, M, 4,
/*11*/M, M, 100, M, 83, M, M2, 12, 87, M, M, 57, M2, M, M3, M,
/*12*/M2, 97, 82, M2, 78, M2, M2, 1, 96, M, M, M, M, M, M3, M2,
/*13*/94, M, M2, M3, M2, M, M3, M, M2, M, 79, M, 69, M, M4, M,
/*14*/M2, 93, 92, M, 91, M, M2, 8, 90, M2, M2, M, M, M, M, M4,
/*15*/89, M, M, M3, M2, M3, M3, M, M, M, M3, M2, M3, M2, M, M3,
/*16*/86, M, M2, M3, M2, M, M3, M, M2, M, M3, M, M3, M, M, M3,
/*17*/M, M, M3, M2, M3, M2, M4, M, 60, M, M2, M3, M4, M, M, M2,
/*18*/M2, 88, 85, M2, 84, M, M2, 55, 81, M2, M2, M3, M2, M3, M3, M4,
/*19*/77, M, M, M, M2, M3, M, M, M2, M3, M3, M4, M3, M2, M, M,
/*1a*/74, M, M2, M3, M, M, M3, M, M, M, M3, M, M3, M, M4, M3,
/*1b*/M2, 70, 107, M4, 65, M2, M2, M, 127, M, M, M, M2, M3, M3, M,
/*1c*/80, M2, M2, 72, M, 119, 118, M, M2, 126, 76, M, 125, M, M4, M3,